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PIC18F97J94 FAMILY

DS30575A-page 282  2012 Microchip Technology Inc.

14.1 Timer0 Operation

Timer0 can operate in one of these two modes:

• As an 8-bit (T08BIT = 1) or 16-bit (T08BIT = 0)

timer

• As an asynchronous 8-bit (T08BIT = 1) or 16-bit

(T08BIT = 0) counter

14.1.1 TIMER MODE

In Timer mode, Timer0 either increments every CPU

clock cycle, or every instruction cycle, depending on

the clock select bit, TMR0CS<1:0> (T0CON<7:6>).

14.1.2 COUNTER MODE

In this mode, Timer0 is incremented via a rising or fall-

ing edge of an external source on the T0CKI pin. The

clock select bits, TMR0CS<1:0>, must be set to ‘1x’.

14.2 Timer0 Reads and Writes in 16-Bit

Mode

TMR0H is not the actual high byte of Timer0 in 16-bit

mode. It is actually a buffered version of the real high

byte of Timer0, which is not directly readable nor

writable (see Figure 14-2). TMR0H is updated with the

contents of the high byte of Timer0 during a read of

TMR0L. This provides the ability to read all 16 bits of

Timer0 without having to verify that the read of the high

and low byte were valid, due to a rollover between

successive reads of the high and low byte.

Similarly, a write to the high byte of Timer0 must also

take place through the TMR0H Buffer register. The high

byte is updated with the contents of TMR0H when a

write occurs to TMR0L. This allows all 16 bits of Timer0

to be updated at once.

FIGURE 14-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE)

FIGURE 14-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE)

Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.

T0CKI Pin

T0SE

T0CS

FOSC/4

Sync with

Internal

Clocks

TMR0L

(2 TCY Delay)

Internal Data Bus

PSA

T0PS<2:0>

Set

TMR0IF

on Overflow

Programmable

Prescaler