Datasheet

 2012 Microchip Technology Inc. DS30575A-page 259
PIC18F97J94 FAMILY
13.6 BIAS CONFIGURATIONS
PIC18F97J94 family devices have four distinct circuit
configurations for LCD bias generation:
• M0: Regulator with Boost
• M1: Regulator without Boost
• M2: Resistor Ladder with Software Contrast
• M3: Resistor Ladder with Hardware Contrast
13.6.1 M0 (REGULATOR WITH BOOST)
In M0 operation, the LCD charge pump feature is
enabled. This allows the regulator to generate voltages
up to +3.6V to the LCD (as measured at LCDBIAS3).
M0 uses a flyback capacitor connected between
V
LCAP1 and VLCAP2, as well as filter capacitors on
LCDBIAS0 through LCDBIAS3, to obtain the required
voltage boost (Figure 13-6). The output voltage (VBIAS)
is the difference of the potential between LCDBIAS3
and LCDBIAS0. It is set by the BIAS<2:0> bits which
adjust the offset between LCDBIAS0 and V
SS. The
flyback capacitor (C
FLY) acts as a charge storage ele-
ment for large LCD loads. This mode is useful in those
cases where the voltage requirements of the LCD are
higher than the microcontroller’s V
DD. It also permits
software control of the display’s contrast, by adjust-
ment of bias voltage, by changing the value of the BIAS
bits.
M0 supports static and 1/3 bias types. Generation of
the voltage levels for 1/3 bias is handled automatically,
but must be configured in software.
M0 is enabled by selecting a valid regulator clock
source (CLKSEL<1:0> set to any value except ‘00’)
and setting the CPEN bit. If static bias type is required,
the MODE13 bit must be cleared.
13.6.2 M1 (REGULATOR WITHOUT
BOOST)
M1 operation is similar to M0, but does not use the LCD
charge pump. It can provide V
BIAS up to the voltage
level supplied directly to LCDBIAS3. It can be used in
cases where VDD for the application is expected to
never drop below a level that can provide adequate
contrast for the LCD. The connection of external com-
ponents is very similar to M0, except that LCDBIAS3
must be tied directly to V
DD (Figure 13-6).
The BIAS<2:0> bits can still be used to adjust contrast
in software by changing the V
BIAS. As with M0, chang-
ing these bits changes the offset between LCDBIAS0
and VSS. In M1, this is reflected in the change between
the LCDBIAS0 and the voltage tied to LCDBIAS3.
Thus, if V
DD should change, VBIAS will also change;
where in M0, the level of V
BIAS is constant.
Like M0, M1 supports static and 1/3 bias types.
Generation of the voltage levels for 1/3 bias is handled
automatically but must be configured in software. M1 is
enabled by selecting a valid regulator clock source
(CLKSEL<1:0> set to any value except ‘00’) and clear-
ing the CPEN bit. If 1/3 bias type is required, the
MODE13 bit should also be set.
Note: When the device is put to Sleep while oper-
ating in mode M0 or M1, make sure that the
bias capacitors are fully discharged to get
the lowest Sleep current.