Datasheet

PIC18F97J94 FAMILY
DS30575A-page 256  2012 Microchip Technology Inc.
REGISTER 13-6: LCDREF: LCD REFERENCE LADDER CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LCDIRE — LCDCST2 LCDCST1 LCDCST0 VLCD3PE VLCD2PE VLCD1PE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 LCDIRE: LCD Internal Reference Enable bit
01 = Internal LCD reference is enabled and connected to the internal contrast control circuit
00 = Internal LCD reference is disabled
bit 6 Unimplemented: Read as ‘0’
bit 5-3 LCDCST<2:0>: LCD Contrast Control bits
Selects the Resistance of the LCD Contrast Control Resistor Ladder:
111 = Resistor ladder is at maximum resistance (minimum contrast)
110 = Resistor ladder is at 6/7th of maximum resistance
101 = Resistor ladder is at 5/7th of maximum resistance
100 = Resistor ladder is at 4/7th of maximum resistance
011 = Resistor ladder is at 3/7th of maximum resistance
010 = Resistor ladder is at 2/7th of maximum resistance
001 = Resistor ladder is at 1/7th of maximum resistance
000 = Minimum resistance (maximum contrast); resistor ladder is shorted
bit 2 VLCD3PE: Bias3 Pin Enable bit
01 = BIAS3 level is connected to the external pin, LCDBIAS3
00 = BIAS3 level is internal (internal resistor ladder)
bit 1 VLCD2PE: Bias2 Pin Enable bit
01 = BIAS2 level is connected to the external pin, LCDBIAS2
00 = BIAS2 level is internal (internal resistor ladder)
bit 0 VLCD1PE: Bias1 Pin Enable bit
01 = BIAS1 level is connected to the external pin, LCDBIAS1
00 = BIAS1 level is internal (internal resistor ladder)