Datasheet

PIC18F97J94 FAMILY
DS30575A-page 236  2012 Microchip Technology Inc.
FIGURE 12-1: SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR
D
Q
MDBIT
MDMIN
MSSP1 (SDO)
MSSP2 (SDO)
EUSART1 (TX
X)
EUSART2 (TX
X)
EUSART3 (TX
X)
EUSART4 (TX
X)
VSS
MDCIN1
MDCIN2
REFO1 Clock
ECCP1
ECCP2
ECCP3
CCP4
0000
0001
0010
0011
0100
0101
0110
0111
1000
1011
1001
MDCH<3:0>
MDSRC<3:0>
MDCL<3:0>
ECCP1
ECCP2
SYNC
MDCHPOL
MDCLPOL
D
Q
1
0
SYNC
1
0
MDCHSYNC
MDCLSYNC
MDOUT
MDOPOL
MDOE
CARH
CARL
EN
MDEN
Data Signal
Modulator
MOD
CCP5
CCP6
1010
CCP7
CCP8
1100
1101
1110
CCP9
1111
CCP10
REFO2 Clock
System Clock
ECCP3
CCP4
CCP5
CCP6
CCP7
CCP8
VSS
MDCIN1
MDCIN2
REFO1 Clock
ECCP1
ECCP2
ECCP3
CCP4
CCP5
CCP6
CCP7
CCP8
CCP9
CCP10
REFO2 C
LOCK
System Clock
Switches Between
PORT Function
and DSM Output
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1101
1011
1100
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1011
1001
1010
1100
1101
1110
1111