Datasheet
PIC18F97J94 FAMILY
DS30575A-page 232 2012 Microchip Technology Inc.
11.15.3.3 I/O Mapping
While most peripheral signals are defined as either
input or output, some peripheral signals switch
between input and output: UnRX_DT, UnTX_CK, PBIO
and CCP. Most commonly, these signals are mapped
so that both the input and output map to the same RPn
pin. If desired, the input and output can be mapped to
separate pins. For standard peripheral operation,
ensure that both the input and output mapping
configurations select the same RPn pin.
11.15.3.4 Mapping Limitations
The control schema of Peripheral Select Pins is not lim-
ited to a small range of fixed peripheral configurations.
There are no mutual or hardware enforced lockouts
between any of the peripheral mapping SFRs. While
such mappings may be technically possible from a
configuration point of view, the user must ensure the
selected configurations are supportable from an
electrical point of view.
11.15.4 CONTROLLING CONFIGURATION
CHANGES
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. PIC18F97J94 devices include two features to
prevent alterations to the peripheral map:
• Continuous state monitoring
• Configuration bit remapping lock
PPS-Lite Output Peripheral Group 4n + 2 PPS-Lite Output Peripheral Group 4n +3
(1) To Map this RPn Pin (4) to the Associated RPOR Register (1) To Map this RPn Pin (4) to the Associated RPOR Register
RP2 RPOR2_3<3:0> RP3 RPOR2_3<7:4>
RP6 RPOR6_7<3:0> RP7 RPOR6_7<7:4>
RP10 RPOR10_11<3:0> RP11 RPOR10_11<7:4>
RP14 RPOR14_15<3:0> RP15 RPOR14_15<7:4>
RP18 RPOR18_19<3:0> RP19 RPOR18_19<7:4>
RP22 RPOR22_23<3:0> RP23 RPOR22_23<7:4>
RP26 RPOR26_27<3:0> RP27 RPOR26_27<7:4>
RP30 RPOR30_31<3:0> RP31 RPOR30_31<7:4>
RP34 RPOR34_35<3:0> RP35 RPOR34_35<7:4>
RP38 RPOR38_39<3:0> RP39 RPOR38_39<7:4>
RP42 RPOR42_43<3:0> RP43 RPOR42_43<7:4>
RP46 RPOR46<3:0>
(2) with this Output Signal (3) Write this Corresponding Value (2) with this Output Signal (3) Write this Corresponding Value
Disabled h’0 Disabled h’0
U1TX_CK h’1 U1RX_DT h’1
U2RX_DT h’2 U2TX_CK h’2
U3BCLK h’3 SCK1 h’3
U4BCLK h’4 ECCP1/P1A h’4
SCK2 h’5 ECCP2/P2A h’5
P1B h’6 P3D h’6
P2B h’7 MDOUT h’7
ECCP3/P3A h’8 CCP4 h’8
CCP6 h’9 C3OUT h’9
CCP10 h’A Unused h’A
Unused h’B Unused h’B
Unused h’C Unused h’C
PBIO2 h’D PBIO3 h’D
PBIO6 h’E PBIO7 h’E
Reserved h’F Reserved h’F
TABLE 11-14: PPS-LITE OUTPUT (CONTINUED)