Datasheet

PIC18F97J94 FAMILY
DS30575A-page 220  2012 Microchip Technology Inc.
11.12 PORTL, LATL and TRISL Registers
PORTL is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction and Output Latch registers are
TRISL and LATL.
All pins on PORTL are implemented with Schmitt Trig-
ger input buffers. Each pin is individually configurable
as an input or output.
Each of the PORTL pins has a weak internal pull-up.
The pull-ups are provided to keep the inputs at a known
state for the external memory interface while powering
up. A single control bit can turn off all the pull-ups. This
is performed by clearing bit, RLPU (PADCFG<0>).
The weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on any device Reset.
EXAMPLE 11-11: INITIALIZING PORTL
Note: PORTL is available only on 100-pin
devices.
BANKSEL PORTL ; select correct bank
CLRF PORTL ; Initialize PORTL by
; clearing output latches
CLRF LATL ; Alternate method
; to clear output latches
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISL ; Set RL3:RL0 as inputs
; RL5:RL4 as output
; RL7:RL6 as inputs
TABLE 11-11: PORTL FUNCTIONS
Pin Name Function
TRIS
Setting
I/O I/O Type Description
RL0/SEG48 RL0 0 O DIG LATL<0> data output.
1 I ST PORTL<0> data input.
SEG48 0 O ANA LCD Segment 48 output; disables all other pin functions.
RL1/SEG49 RL1 0 O DIG LATL<1> data output.
1 I ST PORTL<1> data input.
SEG49 0 O ANA LCD Segment 49 output; disables all other pin functions.
RL2/SEG50 RL2 0 O DIG LATL<2> data output.
1 I ST PORTL<2> data input.
SEG50 0 O ANA LCD Segment 50 output; disables all other pin functions.
RL3/SEG51 RL3 0 O DIG LATL<3> data output.
1 I ST PORTL<3> data input.
SEG51 0 O ANA LCD Segment 51 output; disables all other pin functions.
RL4/SEG52 RL4 0 O DIG LATL<4> data output.
1 I ST PORTL<4> data input.
SEG52 0 O ANA LCD Segment 52 output; disables all other pin functions.
RL5/SEG53 RL5 0 O DIG LATL<5> data output.
1 I ST PORTL<5> data input.
SEG53 0 O ANA LCD Segment 53 output; disables all other pin functions.
RL6/SEG54 RL6 0 O DIG LATL<6> data output.
1 I ST PORTL<6> data input.
SEG54 0 O ANA LCD Segment 54 output; disables all other pin functions.
RL7/SEG55 RL7 0 O DIG LATL<7> data output.
1 I ST PORTL<7> data input.
SEG55 0 O ANA LCD Segment 55 output; disables all other pin functions.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).