Datasheet

 2012 Microchip Technology Inc. DS30575A-page 217
PIC18F97J94 FAMILY
11.10 PORTJ, LATJ and TRISJ Registers
PORTJ is an 8-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISJ and LATJ.
All pins on PORTJ are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
When the external memory interface is enabled, all of
the PORTJ pins function as control outputs for the inter-
face. This occurs automatically when the interface is
enabled by clearing the EBDIS control bit
(MEMCON<7>). The TRISJ bits are also overridden.
Each of the PORTJ pins has a weak internal pull-up.
The pull-ups are provided to keep the inputs at a known
state for the external memory interface while powering
up. A single control bit can turn off all the pull-ups. This
is performed by clearing bit, RJPU (PADCFG<2>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
EXAMPLE 11-9: INITIALIZING PORTJ
Note: PORTJ is available only on 80-pin and
100-pin devices.
Note: These pins are configured as digital inputs
on any device Reset.
CLRF PORTJ ; Initialize PORTJ by
; clearing output latches
CLRF LATJ ; Alternate method
; to clear output latches
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISJ ; Set RJ3:RJ0 as inputs
; RJ5:RJ4 as output
; RJ7:RJ6 as inputs
TABLE 11-9: PORTJ FUNCTIONS
Pin Name Function
TRIS
Setting
I/O I/O Type Description
RJ0/SEG32/
ALE
RJ0 0 O DIG LATJ<0> data output.
1 I ST PORTJ<0> data input.
SEG32 0 O ANA LCD Segment 32 output; disables all other pin functions.
ALE x O DIG External Memory Bus Address Latch Enable (ALE) signal.
RJ1/SEG33/OE
RJ1 0 O DIG LATJ<1> data output.
1 I ST PORTJ<1> data input.
SEG33 0 O ANA LCD Segment 33 output; disables all other pin functions.
OE
x O DIG External Memory Bus Address Latch Enable (OE) signal.
RJ2/SEG34/
WRL
RJ2 0 O DIG LATJ<2> data output.
1 I ST PORTJ<2> data input.
SEG34 0 O ANA LCD Segment 34 output; disables all other pin functions.
WRL
x O DIG External Memory Bus Write Low (WRL) signal.
RJ3/SEG35/
WRH
RJ3 0 O DIG LATJ<3> data output.
1 I ST PORTJ<3> data input.
SEG35 0 O ANA LCD Segment 35 output; disables all other pin functions.
WRH
x O DIG External Memory Bus Write High (WRH) signal.
RJ4/SEG39/
BA0
RJ4 0 O DIG LATJ<4> data output.
1 I ST PORTJ<4> data input.
SEG39 0 O ANA LCD Segment 39 output; disables all other pin functions.
BA0 x O DIG External Memory Bus Byte Access 0 (BA0) signal.
RJ5/SEG38/CE
RJ5 0 O DIG LATJ<5> data output.
1 I ST PORTJ<5> data input.
SEG38 0 O ANA LCD Segment 38 output; disables all other pin functions.
CE
x O DIG External Memory Bus Chip Enable (CE) signal.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).