Datasheet

 2012 Microchip Technology Inc. DS30575A-page 213
PIC18F97J94 FAMILY
11.8 PORTG, LATG and TRISG
Registers
PORTG width varies depending on pin count. For
64- and 80-pin devices, PORTG is a 6-bit wide, bidirec-
tional port. For 100-pin devices, PORTG is an 8-bit wide
bidirectional port. The corresponding Data Direction and
Output Latch registers are TRISG and LATG.
PORTG is multiplexed with the EUSART, and CCP,
ECCP, Analog, Comparator, RTCC and Timer input
functions (Table 11-7). When operating as I/O, all
PORTG pins have Schmitt Trigger input buffers. The
open-drain functionality for the CCPx and EUSARTx
can be configured using ODCONx.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS bit
settings. The pin override value is not loaded into the
TRIS register. This allows read-modify-write of the TRIS
register without concern due to peripheral overrides.
EXAMPLE 11-7: INITIALIZING PORTG
CLRF PORTG ; Initialize PORTG by
; clearing output
; data latches
BCF CM1CON, CON ; disable
; comparator 1
CLRF LATG ; Alternate method
; to clear output
; data latches
BANKSEL ANCON2 ; Select bank with ACON2 register
MOVLW 0F0h ; make AN16 to AN19
; digital
MOVWF ANCON2
BANKSEL TRISG ; Select bank with TRISG register
MOVLW 04h ; Value used to
; initialize data
; direction
MOVWF TRISG ; Set RG1:RG0 as
; outputs
; RG2 as input
; RG4:RG3 as inputs
TABLE 11-7: PORTG FUNCTIONS
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
RG0/RP46/AN8/
SEG28/COM4
RG0
0
O DIG LATG<0> data output; not affected by analog input.
1
I ST PORTG<0> data input; disabled when analog input is enabled.
RP46
x
x DIG Reconfigurable Pin 46 for PPS-Lite; TRIS must be set to match
input/output of module.
AN8
1
I ANA A/D Input Channel 8. Default input configuration on POR; does not
affect digital output.
SEG28
0
O ANA LCD Segment 28 output; disables all other pin functions.
COM4
x
O ANA LCD Common 4 output; disables all other outputs.
RG1/RP39/
AN19/SEG29/
COM5
RG1
0
O DIG LATG<1> data output; not affected by analog input.
1
I ST PORTG<1> data input; disabled when analog input is enabled.
RP39
x
x DIG Reconfigurable Pin 39 for PPS-Lite; TRIS must be set to match
input/output of module.
AN19
1
I ANA A/D Input Channel 19. Default input configuration on POR; does not
affect digital output.
SEG29
0
O ANA LCD Segment 29 output; disables all other pin functions.
COM5
x
O ANA LCD Common 5 output; disables all other outputs.
RG2/RP42/
C3INA/AN18/
SEG30/COM6
RG2
0
O DIG LATG<2> data output; not affected by analog input.
1
I ST PORTG<2> data input; disabled when analog input is enabled.
RP42
x
x DIG Reconfigurable Pin 42 for PPS-Lite; TRIS must be set to match
input/output of module.
C3INA
1
I ANA Comparator 3 Input A.
AN18
1
I ANA A/D Input Channel 18. Default input configuration on POR; does not
affect digital output.
SEG30
0
O ANA LCD Segment 30 output; disables all other pin functions.
COM6
x
O ANA LCD Common 6 output; disables all other outputs.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).