Datasheet

PIC18F97J94 FAMILY
DS30575A-page 210  2012 Microchip Technology Inc.
RE3/REFO1/
RP33/COM0/
AD11
RE3 0 O DIG LATE<3> data output.
1 I ST PORTE<3> data input.
REFO1 0 O DIG Reference Clock Output 1.
RP33 x x DIG Reconfigurable Pin 33 for PPS-Lite; TRIS must be set to match
input/output of module.
COM0 x O ANA LCD Common 0 output; disables all other outputs.
AD11 x I/O ST/DIG External Memory Bus Address Line 11.
RE4/RP32/
COM1/AD12
RE4 0 O DIG LATE<4> data output.
1 I ST PORTE<4> data input.
RP32 x x DIG Reconfigurable Pin 32 for PPS-Lite; TRIS must be set to match
input/output of module.
COM1 x O ANA LCD Common 1 output; disables all other outputs.
AD12 x I/O ST/DIG External Memory Bus Address Line 12.
RE5/RP37/
COM2/AD13
RE5 0 O DIG LATE<5> data output.
1 I ST PORTE<5> data input.
RP37 x x DIG Reconfigurable Pin 37 for PPS-Lite; TRIS must be set to match
input/output of module.
COM2 x O ANA LCD Common 2 output; disables all other outputs.
AD13 x I/O ST/DIG External Memory Bus Address Line 13.
RE6/RP34/
COM3/AD14
RE6 0 O DIG LATE<6> data output.
1 I ST PORTE<6> data input.
RP34 x x DIG Reconfigurable Pin 34 for PPS-Lite; TRIS must be set to match
input/output of module.
COM3 x O ANA LCD Common 3 output; disables all other outputs.
AD14 x I/O ST/DIG External Memory Bus Address Line 14.
RE7/RP31/
LCDBIAS0/
AD15
RE7 0 O DIG LATE<7> data output.
1 I ST PORTE<7> data input.
RP31 x x DIG Reconfigurable Pin 31 for PPS-Lite; TRIS must be set to match
input/output of module.
LCDBIAS0 x I ANA LCD Module Bias Voltage Input 0.
AD15 x I/O ST/DIG External Memory Bus Address Line 15.
TABLE 11-5: PORTE FUNCTIONS (CONTINUED)
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).