Datasheet

 2012 Microchip Technology Inc. DS30575A-page 207
PIC18F97J94 FAMILY
11.5 PORTD, LATD and
TRISD Registers
PORTD is an 8-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISD and LATD.
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Each of the PORTD pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by setting bit, RDPU (PADCFG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on all device Resets.
On 80-pin and 100-pin devices, PORTD is multiplexed
with the system bus as part of the external memory
interface. I/O port and other functions are only available
when the interface is disabled by setting the EBDIS bit
(MEMCON<7>). When the interface is enabled,
PORTD is the low-order byte of the multiplexed
Address/Data bus (AD<7:0>). The TRISD bits are also
overridden.
PORTD can also be configured as an 8-bit wide micro-
processor port (Parallel Slave Port) by setting control
bit, PSPMODE (PSPCON<4>). In this mode, the input
buffers are TTL. For additional information, see
Section 11.13 “Parallel Slave Port”.
PORTD also has I
2
C functionality on RD5 and RD6.
EXAMPLE 11-4: INITIALIZING PORTD
Note: These pins are configured as digital inputs
on any device Reset.
CLRF PORTD ; Initialize PORTD by
; clearing output
; data latches
CLRF LATD ; Alternate method
; to clear output
; data latches
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISD ; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
TABLE 11-4: PORTD FUNCTIONS
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
RD0/PSP0/
RP20/SEG0/AD0
RD0 0 O DIG LATD<0> data output.
1 I ST PORTD<0> data input.
PSP0 x I/O ST/DIG Parallel Slave Port Data Bus Bit 0.
RP20 x x DIG Reconfigurable Pin 20 for PPS-Lite; TRIS must be set to match
input/output of module.
SEG0 0 O ANA LCD Segment 0 output; disables all other pin functions.
AD0 x I/O ST/DIG External Memory Bus Address Line 0.
RD1/PSP1/
RP21/SEG1/AD1
RD1 0 O DIG LATD<1> data output.
1 I ST PORTD<1> data input.
PSP1 x I/O ST/DIG Parallel Slave Port Data Bus Bit 1.
RP21 x x DIG Reconfigurable Pin 21 for PPS-Lite; TRIS must be set to match
input/output of module.
SEG1 0 O ANA LCD Segment 1 output; disables all other pin functions.
AD1 x I/O ST/DIG External Memory Bus Address Line 1.
RD2/PSP2/
RP22/SEG2/AD2
RD2 0 O DIG LATD<2> data output.
1 I ST PORTD<2> data input.
PSP2 x I/O ST/DIG Parallel Slave Port Data Bus Bit 2.
RP22 x x DIG Reconfigurable Pin 22 for PPS-Lite; TRIS must be set to match
input/output of module.
SEG2 0 O ANA LCD Segment 2 output; disables all other pin functions.
AD2 x I/O ST/DIG External Memory Bus Address Line 2.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
I2C = I
2
C™/SMBus, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).