Datasheet

PIC18F97J94 FAMILY
DS30575A-page 202  2012 Microchip Technology Inc.
RA3/AN3/V
REF+/RP3 RA3 0 O DIG LATA<3> data output; not affected by analog input.
1 I ST PORTA<3> data input; disabled when analog input is enabled.
AN3 1 I ANA A/D Input Channel 3. Default input configuration on POR; does not
affect digital output.
V
REF+ 1 I ANA A/D and Comparator High Reference Voltage input.
RP3 x x DIG Reconfigurable Pin 3 for PPS-Lite; TRIS must be set to match
input/output of module.
RA4/AN6/RP4/SEG14 RA4 0 O DIG LATA<4> data output; not affected by analog input.
1 I ST PORTA<4> data input; disabled when analog input is enabled.
AN6 1 I ANA A/D Input Channel 6. Default input configuration on POR; does not
affect digital output.
RP4 x x DIG Reconfigurable Pin 4 for PPS-Lite; TRIS must be set to match
input/output of module.
SEG14 0 O ANA LCD Segment 14 output; disables all other pin functions.
RA5/AN4/RP5/LVDIN/
C1INA/C2INA/C3INA/
SEG15
RA5 0 O DIG LATA<5> data output; not affected by analog input.
1 I ST PORTA<5> data input; disabled when analog input is enabled.
AN4 1 I ANA A/D Input Channel 4. Default input configuration on POR; does not
affect digital output.
RP5 x x DIG Reconfigurable Pin 5 for PPS-Lite; TRIS must be set to match
input/output of module.
LVDIN 1 I ANA High/Low-Voltage Detect (HLVD) external trip point input.
C1INA 1 I ANA Comparator 1 Input A.
C2INA 1 I ANA Comparator 2 Input A.
C3INA 1 I ANA Comparator 3 Input A.
SEG15 0 O ANA LCD Segment 15 output; disables all other pin functions.
RA6/RP6/CLKO/OSC2 RA6 0 O DIG LATA<6> data output; disabled when OSC2 Configuration bit is set.
1 I ST PORTA<6> data input; disabled when OSC2 Configuration bit is set.
RP6 x x DIG Reconfigurable Pin 6 for PPS-Lite; TRIS must be set to match
input/output of module.
CLKO x O DIG System cycle clock output (F
OSC/4, EC and Internal Oscillator
modes).
OSC2 x O ANA Main oscillator feedback output connection (HS, MS and LP
modes).
RA7/RP10/CLKI/OSC1 RA7 0 O DIG LATA<7> data output; disabled when OSC2 Configuration bit is set.
1 I ST PORTA<7> data input; disabled when OSC2 Configuration bit is set.
RP10 x x DIG Reconfigurable Pin 10 for PPS-Lite; TRIS must be set to match
input/output of module.
CLKI x O DIG Main external clock source input (EC modes).
OSC1 x O ANA Main oscillator input connection (HS, MS and LP modes).
TABLE 11-1: PORTA FUNCTIONS (CONTINUED)
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).