Datasheet

 2012 Microchip Technology Inc. DS30575A-page 201
PIC18F97J94 FAMILY
11.2 PORTA, LATA and TRISA
Registers
PORTA is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction and Output Latch registers are
TRISA and LATA.
All PORTA pins have Schmitt Trigger input levels and
full CMOS output drivers.
RA<5:0> are multiplexed with analog inputs for the A/D
Converter.
The operation of the analog inputs as A/D Converter
inputs is selected by clearing or setting the ANSELx
control bits in the ANCON1 register. The corresponding
TRISA bits control the direction of these pins, even
when they are being used as analog inputs. The user
must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
OSC2/CLKO/RA6 and OSC1/CLKI/RA7 normally
serve as the external circuit connections for the Exter-
nal (Primary) Oscillator circuit (HS Oscillator modes),
or the external clock input and output (EC Oscillator
modes). In these cases, RA6 and RA7 are not available
as digital I/O, and their corresponding TRIS and LAT
bits are read as ‘0’. When the device is configured to
use either the FRC or LPRC Internal Oscillators as the
default oscillator mode, RA6 and RA7 are automatically
configured as digital I/O; the oscillator and clock
in/clock out functions are disabled.
EXAMPLE 11-1: INITIALIZING PORTA
Note: RA<5:0> are configured as analog inputs
on any Reset and are read as ‘0’.
CLRF PORTA ; Initialize PORTA by
; clearing output latches
CLRF LATA ; Alternate method to
; clear output data latches
BANKSEL ANCON1 ; Select bank with ANCON1 register
MOVLW 00h ; Configure A/D
MOVWF ANCON1 ; for digital inputs
BANKSEL TRISA ; Select bank with TRISA register
MOVLW 0BFh ; Value used to initialize
; data direction
MOVWF TRISA ; Set RA<7, 5:0> as inputs,
; RA<6> as output
TABLE 11-1: PORTA FUNCTIONS
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
RA0/AN0/AN1-/RP0/
SEG19
RA0 0 O DIG LATA<0> data output; not affected by analog input.
1 I ST PORTA<0> data input; disabled when analog input is enabled.
AN0 1 I ANA A/D Input Channel 0. Default input configuration on POR; does not
affect digital output.
AN1- 1 I ANA Quasi-differential A/D negative input channel.
RP0 x x DIG Reconfigurable Pin 0 for PPS-Lite; TRIS must be set to match
input/output of the module.
SEG19 0 O ANA LCD Segment 19 output; disables all other pin functions.
RA1/AN1/RP1/SEG18 RA1 0 O DIG LATA<1> data output; not affected by analog input.
1 I ST PORTA<1> data input; disabled when analog input is enabled.
AN1 1 I ANA A/D Input Channel 1. Default input configuration on POR; does not
affect digital output.
RP1 x x DIG Reconfigurable Pin 1 for PPS-Lite; TRIS must be set to match
input/output of module.
SEG18 0 O ANA LCD Segment 18 output; disables all other pin functions.
RA2/AN2/V
REF-/RP2/
SEG21
RA2 0 O DIG LATA<2> data output; not affected by analog input.
1 I ST PORTA<2> data input; disabled when analog input enabled.
AN2 1 I ANA A/D Input Channel 2. Default input configuration on POR; does not
affect digital output.
V
REF- 1 I ANA A/D and Comparator Low Reference Voltage input.
RP2 x x DIG Reconfigurable Pin 2 for PPS-Lite; TRIS must be set to match
input/output of module.
SEG21 0 O ANA LCD Segment 21 output; disables all other pin functions.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).