Datasheet

 2012 Microchip Technology Inc. DS30575A-page 199

PIC18F97J94 FAMILY

11.1.3 OPEN-DRAIN OUTPUTS

The output pins for several peripherals are also

equipped with a configurable, open-drain output option.

This allows the peripherals to communicate with

external digital logic, operating at a higher voltage

level, without the use of level translators.

The open-drain option is implemented on the

EUSARTs, the MSSPx modules (in SPI mode) and the

CCP modules. These modules are assigned to an I/O

pin using the PPS (Peripheral Pin Select) feature. The

open-drain option is enabled by setting the open-drain

control bits in the ODCON1 and ODCON2 registers.

When the open-drain option is required, the output pin

must also be tied through an external pull-up resistor,

provided by the user, to a higher voltage level, up to 5V

(Figure 11-2). When a digital logic high signal is output,

it is pulled up to the higher voltage level.

FIGURE 11-2: USING THE OPEN-DRAIN

OUTPUT (USART SHOWN

AS EXAMPLE)

TXX

+5V

3.3V

(at logic ‘1’)

3.3V

DD 5V

PIC18F97J94

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ECCP2OD ECCP1OD USART4OD USART3OD USART2OD USART1OD SSP2OD SSP1OD

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ECCP2OD: ECCP2 Open Drain Output Enable bit