Datasheet

 2012 Microchip Technology Inc. DS30575A-page 193
PIC18F97J94 FAMILY
10.9 INTx Pin Interrupts
External interrupts on the RB0/INT0, RB1/INT1,
RB2/INT2 and RB3/INT3 pins are edge-triggered. If the
corresponding INTEDGx bit in the INTCON2 register is
set (= 1), the interrupt is triggered by a rising edge. If
that bit is clear, the trigger is on the falling edge.
When a valid edge appears on the RBx/INTx pin, the
corresponding flag bit, INTxIF, is set. This interrupt can
be disabled by clearing the corresponding enable bit,
INTxIE. Before re-enabling the interrupt, the flag bit
(INTxIF) must be cleared in software in the Interrupt
Service Routine.
All external interrupts (INT0, INT1, INT2 and INT3) can
wake-up the processor from the power-managed
modes if bit, INTxIE, was set prior to going into the
power-managed modes. If the Global Interrupt Enable
bit (GIE) is set, the processor will branch to the interrupt
vector following wake-up.
The interrupt priority for INT1, INT2 and INT3 is
determined by the value contained in the Interrupt
Priority bits, INT1IP (INTCON3<6>), INT2IP
(INTCON3<7>) and INT3IP (INTCON2<1>).
There is no priority bit associated with INT0. It is always
a high-priority interrupt source.
10.10 TMR0 Interrupt
In 8-bit mode (the default), an overflow in the TMR0
register (FFh  00h) will set flag bit, TMR0IF. In 16-bit
mode, an overflow in the TMR0H:TMR0L register pair
(FFFFh  0000h) will set TMR0IF.
The interrupt can be enabled/disabled by setting/clearing
enable bit, TMR0IE (INTCON<5>). Interrupt priority for
Timer0 is determined by the value contained in the inter-
rupt priority bit, TMR0IP (INTCON2<2>). For further
details on the Timer0 module, see Section 14.0 “Timer0
Module”.
10.11 Edge-Selectable
Interrupt-on-Change
Interrupt-on-change pins are selected via the PPS
register settings and have the option of generating an
interrupt on positive or negative transitions, or both.
Positive edge events are enabled by setting the corre-
sponding bits in the IOCP register, while negative edge
events are enabled by setting the corresponding bits in
the IOCN register. For compatibility with the previous
interrupt-on-change feature, both the IOCP and IOCN
bits should be set. The interrupt can be enabled by
setting/clearing the IOCIE (INTCON<3>) bit. Each
individual pin can be disabled by clearing both of the
corresponding IOCN/IOCP bits. A change event (either
positive or negative edge) will cause the corresponding
IOCF flag to be set.
Interrupt priority for the edge selectable
interrupt-on-change is determined by the interrupt
priority bit, IOCIP (INTCON2<0>).