Datasheet

 2012 Microchip Technology Inc. DS30575A-page 191
PIC18F97J94 FAMILY
REGISTER 10-21: IPR6: PERIPHERAL INTERRUPT PRIORITY REGISTER 6
R/W-1 R/W-1 R/W-1 R/W-1 U-O R/W-1 R/W-1 R/W-1
RC4IP TX4IP RC3IP TX3IP
— CMP3IP CMP2IP CMP1IP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RCP4IP: EUSART4 Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6 TX4IP: EUSART4 Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 RC3IP: EUSART3 Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4 TX3IP: EUSART3 Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3 Unimplemented: Read as ‘0’
bit 2 CMP3IP: CMP3 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 CMP2IP: CMP2 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 CMP1IP: CMP1 Interrupt Priority bit
1 = High priority
0 = Low priority