Datasheet

PIC18F97J94 FAMILY
DS30575A-page 14  2012 Microchip Technology Inc.
FIGURE 1-1: 64-PIN DEVICE BLOCK DIAGRAM
PORTA
Data Latch
Data Memory
(4 Kbytes)
Address Latch
Data Address<12>
12
Access
BSR
FSR0
FSR1
FSR2
inc/dec
logic
Address
4
12
4
PCH PCL
PCLATH
8
31-Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
8
BITOP
8
8
ALU<8>
Address Latch
Program Memory
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
12
3
PCLATU
PCU
Note 1: See Table 1-4 for I/O port pin descriptions.
2: RA6 and RA7 are only available as digital I/O in select oscillator modes. For more information, see Section 3.0 “Oscillator
Configurations”.
EUSART1
Comparator
MSSP1/2
3/52/4/6/8
CTMUTimer1
A/D
10/12-Bit
W
Instruction Bus <16>
STKPTR
Bank
8
State Machine
Control Signals
Decode
8
8
EUSART2
ROM Latch
PORTC
PORTD
PORTE
PORTF
PORTG
RA<7:0>
(1,2)
RC<7:0>
(1)
RD<7:0>
(1)
RE<7:0>
(1)
RF<7:2>
(1)
RG<4:0>
(1)
PORTB
RB<7:0>
(1)
OSC1/CLKI
OSC2/CLKO
V
DD, VSS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
BOR and
HLVD
Precision
Reference
Band Gap
INTRC
Oscillator
Regulator
Voltage
VDDCORE/VCAP
8 MHz
Oscillator
Timer0
4/5/6/7/8/9/10
RTCC
Timer
Timer
1/2/3
CCP
ECCP
1/2/3
USB
EUSART3 EUSART4
IR
Instruction
Decode and
Control
LCD
224 Pixels