Datasheet

 2012 Microchip Technology Inc. DS30575A-page 129
PIC18F97J94 FAMILY
F03h SSP2BUF MSSP2 Receive Buffer/Transmit Register
F02h SSP2ADD MSSP2 Address Register in I
2
C™ Slave Mode. MSSP1 Baud Rate Reload Register in I
2
C Master Mode.
F01h ANCFG
— — — — — VBG6EN VBG2EN VBGEN
F00h DMACON2 DLYCYC3 DLYCYC2 DLYCYC1 DLYCYC0 INTLVL3 INTLVL2 INTLVL1 INTLVL0
EFFh RCSTA4 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
EFEh TXSTA4 CSRC TX9 TXEN SYNC
SENDB BRGH TRMT TX9D
EFDh BAUDCON4 ABDOVF RCIDL RXDTP TXCKP BRG16 IREN WUE ABDEN
EFCh SPBRGH4 EUSART4 Baud Rate Generator High Byte
EFBh SPBRG4 EUSART4 Baud Rate Generator
EFAh RCREG4 EUSART4 Receive Data FIFO
EF9h TXREG4 EUSART4 Transmit Data FIFO
EF8h CTMUCON1 CTMUEN
— CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN TRIGEN
EF7h CTMUCON2 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0
EF6h CTMUCON3 EDG2EN EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0
— —
EF5h CTMUCON4 EDG1EN EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT
EF4h PMD0 CCP10MD CCP9MD CCP8MD CCP7MD CCP6MD CCP5MD CCP4MD ECCP3MD
EF3h PMD1 ECCP2MD ECCP1MD UART4MD UART3MD UART2MD UART1MD SSP2MD SSP1MD
EF2h PMD2 TMR8MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD
EF1h PMD3 TXMMD CTMUMD ADCMD RTCCMD LCDMD PSPMD REFO1MD REFO2MD
EF0h PMD4 CMP1MD CMP2MD CMP3MD USBMD IOCMD LVDMD
—EMBMD
EEFh MDCON MDEN MDOE MDSLR MDOPOL MDO
— —MDBIT
EEEh MDSRC MDSODIS
— — — MDSRC3 MDSRC2 MDSRC1 MDSRC0
EEDh MDCARH MDCHODIS MDCHPOL MDCHSYNC
— MDCH3 MDCH2 MDCH1 MDCH0
EECh MDCARL MDCLODIS MDCLPOL MDCLSYNC
— MDCL3 MDCL2 MDCL1 MDCL0
EEBh ODCON1 ECCP2OD ECCP1OD USART4OD USART3OD USART2OD USART1OD SSP2OD SSP1OD
EEAh ODCON2 CCP10OD CCP9OD CCP8OD CCP7OD CCP6OD CCP5OD CCP4OD ECCP3OD
EE9h TRISK TRISK7 TRISK6 TRISK5 TRISK4 TRISK3 TRISK2 TRISK1 TRISK0
EE8h LATK LATK7 LATK6 LATK5 LATK4 LATK3 LATK2 LATK1 LATK0
EE7h PORTK RK7 RK6 RK5 RK4 RK3 RK2 RK1 RK0
EE6h TRISL TRISL7 TRISL6 TRISL5 TRISL4 TRISL3 TRISL2 TRISL1 TRISL0
EE5h LATL LATL7 LATL6 LATL5 LATL4 LATL3 LATL2 LATL1 LATL0
EE4h PORTL RL7 RL6 RL5 RL4 RL3 RL2 RL1 RL0
EE3h MEMCON EBDIS
—WAIT1WAIT0 — —WM1WM0
EE2h REFO1CON ON
—SIDL OE RSLP — DIVSWEN ACTIVE
EE1h REFO1CON1
— — — — ROSEL3 ROSEL2 ROSEL1 ROSEL0
EE0h REFO1CON2 RODIV7 RODIV6 RODIV5 RODIV4 RODIV3 RODIV2 RODIV1 RODIV0
EDFh REFO1CON3
— RODIV14 RODIV13 RODIV12 RODIV11 RODIV10 RODIV9 RODIV8
EDEh REFO2CON ON
—SIDL OE RSLP — DIVSWEN ACTIVE
EDDh REFO2CON1
— — — — ROSEL3 ROSEL2 ROSEL1 ROSEL0
EDCh REFO2CON2 RODIV7 RODIV6 RODIV5 RODIV4 RODIV3 RODIV2 RODIV1 RODIV0
EDBh REFO2CON3
— RODIV14 RODIV13 RODIV12 RODIV11 RODIV10 RODIV9 RODIV8
EDAh LCDPS WFT BIASMD LCDA WA LP3 LP2 LP1 LP0
ED9h LCDCON LCDEN SLPEN WERR CS1 CS0 LMUX2 LMUX1 LMUX0
ED8h LCDREG CPEN
— BIAS2 BIAS1 BIAS0 MODE13 CLKSEL1 CLKSEL0
ED7h LCDREF LCDIRE
— LCDCST2 LCDCST1 LCDCST0 VLCD3PE VLCD2PE VLCD1PE
ED6h LCDRL LRLAP1 LRLAP0 LRLBP1 LRLBP0
— LRLAT2 LRLAT1 LRLAT0
ED5h LCDSE7 SE63 SE62 SE61 SE60 SE59 SE58 SE57 SE56
ED4h LCDSE6 SE55 SE54 SE53 SE52 SE51 SE50 SE49 SE48
ED3h LCDSE5 SE47 SE46 SE45 SE44 SE43 SE42 SE41 SE40
ED2h LCDSE4 SE39 SE38 S37 SE36 SE35 SE34 SE33 SE32
ED1h LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24
ED0h LCDSE2 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16
TABLE 6-2: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Legend:
— = unimplemented, read as ‘ 0 ’.