Datasheet

PIC18F97J94 FAMILY
DS30575A-page 128  2012 Microchip Technology Inc.
F36h CCPTMRS0 C3TSEL1 C3TSEL0 C2TSEL2 C2TSEL1 C2TSEL0 C1TSEL2 C1TSEL1 C1TSEL0
F35h CCPTMRS1 C7TSEL1 C7TSEL0
— C6TSEL0 — C5TSEL0 C4TSEL1 C4TSEL0
F34h CCPTMRS2
— — —C10TSEL0 — C9TSEL0 C8TSEL1 C8TSEL0
F33h RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
F32h TXSTA2 CSRC TX9 TXEN SYNC
SENDB BRGH TRMT TX9D
F31h BAUDCON2 ABDOVF RCIDL RXDTP TXCKP BRG16 IREN WUE ABDEN
F30h SPBRGH1 EUSART1 Baud Rate Generator High Byte
F2Fh RCSTA3 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
F2Eh TXSTA3 CSRC TX9 TXEN SYNC
SENDB BRGH TRMT TX9D
F2Dh BAUDCON3 ABDOVF RCIDL RXDTP TXCKP BRG16 IREN WUE ABDEN
F2Ch SPBRGH3 EUSART3 Baud Rate Generator High Byte
F2Bh SPBRG3 EUSART3 Baud Rate Generator
F2Ah RCREG3 EUSART3 Receive Data FIFO
F29H TXREG3 EUSART3 Transmit Data FIFO
F28h DSCONL
— — — — — ULPWDIS DSBOR RELEASE
F27h DSCONH DSEN
— — — — — —RTCWDIS
F26h DSWAKEL DSFLT BOR DSULP DSWDT DSRTC DSMCLR DSICD DSPOR
F25h DSWAKEH
— — — — — — —DSINT0
F24h DSGPR0 Deep Sleep General Purpose Register 0
F23h DSGPR1 Deep Sleep General Purpose Register 1
F22h DSGPR2 Deep Sleep General Purpose Register 2
F21h DSGPR3 Deep Sleep General Purpose Register 3
F20h SPBRGH2 EUSART2 Baud Rate Generator High Byte
F1Fh SPBRG2 EUSART2 Baud Rate Generator
F1Eh RCREG2 Receive Data FIFO
F1Dh TXREG2 Transmit Data FIFO
F1Ch PSTR2CON CMPL1 CMPL0
— STRSYNC STRD STRC STRB STRA
F1Bh PSTR3CON CMPL1 CMPL0
— STRSYNC STRD STRC STRB STRA
F1Ah SSP2STAT SMP CKE D/A
PSR/WUA BF
F19h SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
F18h SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
F17h SSP2MSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0
F16h TMR5H Timer5 Register High Byte
F15h TMR5L Timer5 Register Low Byte
F14h T5CON TMR5CS1 TMR5CS0 T5CKPS1 T5CKPS0 SOSCEN T5SYNC
RD16 TMR5ON
F13h T5GCON TMR5GE T5GPOL T5GTM T5GSPM T5GGO/T5
DONE T5GVAL T5GSS1 T5GSS0
F12h CCPR4H Capture/Compare/PWM Register 4 High Byte
F11h CCPR4L Capture/Compare/PWM Register 4 Low Byte
F10h CCP4CON
— — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0
F0Fh CCPR5H Capture/Compare/PWM Register 5 High Byte
F0Eh CCPR5L Capture/Compare/PWM Register 5 Low Byte
F0Dh CCP5CON
— — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0
F0Ch CCPR6H Capture/Compare/PWM Register 6 High Byte
F0Bh CCPR6L Capture/Compare/PWM Register 6 Low Byte
F0Ah CCP6CON
— — DC6B1 DC6B0 CCP6M3 CCP6M2 CCP6M1 CCP6M0
F09h CCPR7H Capture/Compare/PWM Register 7 High Byte
F08h CCPR7L Capture/Compare/PWM Register 7 Low Byte
F07h CCP7CON
— — DC7B1 DC7B0 CCP7M3 CCP7M2 CCP7M1 CCP7M0
F06h TMR4 Timer4 Register
F05h PR4 Timer4 Period Register
F04h T4CON
— T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0
TABLE 6-2: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Legend:
— = unimplemented, read as ‘ 0 ’.