Datasheet

 2012 Microchip Technology Inc. DS30575A-page 125
PIC18F97J94 FAMILY
FCFh TMR1H Timer1 Register High Byte
FCEh TMR1L Timer1 Register Low Byte
FCDh T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 SOSCEN T1SYNC
RD16 TMR1ON
FCCh TMR2 Timer2 Register
FCBh PR2 Timer2 Period Register
FCAh T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
FC9h SSP1BUF MSSP1 Receive Buffer/Transmit Register
FC8h SSP1ADD MSSP1 Address Register in I
2
C™ Slave Mode. MSSP1 Baud Rate Reload Register in I
2
C Master Mode.
FC7h SSP1STAT SMP CKE D/A
PSR/WUA BF
FC6h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
FC5h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
FC4h CMSTAT
— — — — — C3OUT C2OUT C1OUT
FC3h ADCBUF0H A/D Result Register 0 High Byte
FC2h ADCBUF0L A/D Result Register 0 Low Byte
FC1h ADCON1H ADON
— — — — MODE12 FORM1 FORM0
FC0h ADCON1L SSRC3 SSRC2 SSRC1 SSRC0
— ASAM SAMP DONE
FBFh CVRCONH
— — — CVR4 CVR3 CVR2 CVR1 CVR0
FBEh CVRCONL CVREN CVROE CVRPSS1 CVRPSS0
— — — CVRNSS
FBDh ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0
FBCh ECCP1DEL P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0
FBBh CCPR1H Capture/Compare/PWM Register1 High Byte
FBAh CCPR1L Capture/Compare/PWM Register1 Low Byte
FB9h CCP1CON P1M1 P1M0 CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
FB8h PIR5
— ACTORSIF ACTLOCKIF TMR8IF — TMR6IF TMR5IF TMR4IF
FB7h PIE5
— ACTORSIE ACTLOCKIE TMR8IE — TMR6IE TMR5IE TMR4IE
FB6h IPR4 CCP10IP CCP9IP CCP8IP CCP7IP CCP6IP CCP5IP CCP4IP ECCP3IP
FB5h PIR4 CCP10IF CCP9IF CCP8IF CCP7IF CCP6IF CCP5IF CCP4IF ECCP3IF
FB4h PIE4 CCP10IE CCP9IE CCP8IE CCP7IE CCP6IE CCP5IE CCP4IE ECCP3IE
FB3h TMR3H Timer3 Register High Byte
FB2h TMR3L Timer3 Register Low Byte
FB1h T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 SOSCEN T3SYNC
RD16 TMR3ON
FB0h T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/T3
DONE T3GVAL T3GSS1 T3GSS0
FAFh SPBRG1 EUSART1 Baud Rate Generator
FAEh RCREG1 EUSART1 Receive Register
FADh TXREG1 EUSART1 Transmit Register
FACh TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
FABh RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
FAAh T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/T1
DONE T1GVAL T1GSS1 T1GSS0
FA9h IPR6 RC4IP TX4IP RC3IP TX3IP
— CMP3IP CMP2IP CMP1IP
FA8h HLVDCON VDIRMAG BGVST IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0
FA7h PSPCON IBF OBF IBOV PSPMODE
— — — —
FA6h PIR6 RC4IF TX4IF RC3IF TX3IF
— CMP3IF CMP2IF CMP1IF
FA5h IPR3 TMR5GIP LCDIP RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP
FA4h PIR3 TMR5GIF LCDIF RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF
FA3h PIE3 TMR5GIE LCDIE RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE
FA2h IPR2 OSCFIP SSP2IP BCL2IP USBIP BCL1IP HLVDIP TMR3IP TMR3GIP
FA1h PIR2 OSCFIF SSP2IF BCL2IF USBIF BCL1IF HLVDIF TMR3IF TMR3GIF
FA0h PIE2 OSCFIE SSP2IE BCL2IE USBIE BCL1IE HLVDIE TMR3IE TMR3GIE
F9Fh IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP
F9Eh PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF
F9Dh PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE
TABLE 6-2: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Legend:
— = unimplemented, read as ‘ 0 ’.