Datasheet

PIC18F97J94 FAMILY
DS30575A-page 124  2012 Microchip Technology Inc.
TABLE 6-2: REGISTER FILE SUMMARY
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FFFh TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>)
FFEh TOSH Top-of-Stack High Byte (TOS<15:8>)
FFDh TOSL Top-of-Stack Low Byte (TOS<7:0>)
FFCh STKPTR STKFUL STKUNF
—STKPTR
FFBh PCLATU
— — — Holding Register for PC<20:16>
FFAh PCLATH Holding Register for PC<15:8>
FF9h PCL PC Low Byte (PC<7:0>)
FF8h TBLPTRU
— — ACSS Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
FF7h TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
FF6h TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
FF5h TABLAT Program Memory Table Latch
FF4h PRODH Product Register High Byte
FF3h PRODL Product Register Low Byte
FF2h INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF
FF1h INTCON2 RBPU
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP IOCIP
FF0h INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF
FEFh INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
FEEh POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
FEDh POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
FECh PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
FEBh PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – value of
FSR0 offset by W
FEAh FSR0H
— — — — Indirect Data Memory Address Pointer 0 High
FE9h FSR0L Indirect Data Memory Address Pointer 0 Low Byte
FE8h WREG Working Register
FE7h INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
FE6h POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
FE5h POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
FE4h PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
FE3h PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – value of
FSR1 offset by W
FE2h FSR1H
— — — — Indirect Data Memory Address Pointer 1 High
FE1h FSR1L Indirect Data Memory Address Pointer 1 Low Byte
FE0h BSR
— — — — Bank Select Register
FDFh INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
FDEh POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
FDDh POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
FDCh PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
FDBh PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – value of
FSR2 offset by W
FDAh FSR2H
— — — — Indirect Data Memory Address Pointer 2 High
FD9h FSR2L Indirect Data Memory Address Pointer 2 Low Byte
FD8h STATUS
— — —N OV ZDCC
FD7h TMR0H Timer0 Register High Byte
FD6h TMR0L Timer0 Register Low Byte
FD5h T0CON TMR0ON T08BIT T0CS1 T0CS0 PSA T0PS2 T0PS1 T0PS0
FD4h Unimplemented
— — — — — — — —
FD3h OSCCON IDLEN COSC2 COSC1 COSC0
— NOSC2 NOSC1 NOSC0
FD2h IPR5
— ACTORSIP ACTLOCKIP TMR8IP — TMR6IP TMR5IP TMR4IP
FD1h IOCF IOCF7 IOCF6 IOCF5 IOCF4 IOCF3 IOCF2 IOCF1 IOCF0
FD0h RCON IPEN
—CM RI TO PD POR BOR
Legend: — = unimplemented, read as ‘ 0 ’.