Datasheet

 2012 Microchip Technology Inc. DS30575A-page 113
PIC18F97J94 FAMILY
6.0 MEMORY ORGANIZATION
PIC18F97J94 family devices have these types of
memory:
• Program Memory
• Data RAM
As Harvard architecture devices, the data and program
memories use separate busses. This enables
concurrent access of the two memory spaces.
Additional detailed information on the operation of the
Flash program memory is provided in Section 7.0
“Flash Program Memory”.
FIGURE 6-1: MEMORY MAPS FOR PIC18F97J94 FAMILY DEVICES
Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail.
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
000000h
1FFFFFh
01FFFFh
00FFFFh
PC<20:0>
Stack Level 1

Stack Level 31


CALL, CALLW, RCALL,
RETURN, RETFIE, RETLW,
21
User Memory Space
On-Chip
Memory
ADDULNK, SUBULNK
Unimplemented
Read as ‘0’
On-Chip
Memory
007FFFh
Unimplemented
Read as ‘0’
On-Chip
Memory
017FFFh
Config Words
Config Words
Config Words
Config Words
PIC18FX5J94 PIC18FX6J94 PIC18FX6J99 PIC18FX7J94
On-Chip
Memory