Datasheet
2012 Microchip Technology Inc. DS30575A-page 105
PIC18F97J94 FAMILY
CTMUCON1 64-pin 80-pin 100-pin 0000 0000 0000 0000 uuuu uuuu
CTMUCON2 64-pin 80-pin 100-pin 0000 00-- 0000 00-- uuuu uu--
CTMUCON3 64-pin 80-pin 100-pin 0000 0000 0000 0000 uuuu uuuu
PMD0 64-pin 80-pin 100-pin 0000 0000 0000 0000 uuuu uuuu
PMD1 64-pin 80-pin 100-pin 0000 0000 0000 0000 uuuu uuuu
PMD2 64-pin 80-pin 100-pin 0000 0000 0000 0000 uuuu uuuu
PMD3 64-pin 80-pin 100-pin 0000 0000 0000 0000 uuuu uuuu
PMD4 64-pin 80-pin 100-pin 0000 00-- 0000 00-- uuuu uu--
MDCON 64-pin 80-pin 100-pin 0010 0--0 0010 0--0 uuuu u--u
MDSRC 64-pin 80-pin 100-pin 0--- xxxx 0--- uuuu u--- uuuu
MDCARH 64-pin 80-pin 100-pin 0xx- xxxx 0uu- uuuu uuu- uuuu
MDCARL 64-pin 80-pin 100-pin 0xx- xxxx 0uu- uuuu uuu- uuuu
ODCON1 64-pin 80-pin 100-pin 0000 0000 0000 0000 uuuu uuuu
ODCON2 64-pin 80-pin 100-pin 0000 0000 0000 0000 uuuu uuuu
TRISK
64-pin 80-pin 100-pin 1111 1111 1111 1111 uuuu uuuu
LATK
64-pin 80-pin 100-pin xxxx xxxx uuuu uuuu uuuu uuuu
PORTK 64-pin 80-pin 100-pin xxxx xxxx xxxx xxxx uuuu uuuu
TRISL 64-pin 80-pin 100-pin 1111 1111 1111 1111 uuuu uuuu
LATL
64-pin 80-pin 100-pin xxxx xxxx uuuu uuuu uuuu uuuu
PORTL 64-pin 80-pin 100-pin xxxx xxxx xxxx xxxx uuuu uuuu
MEMCON 64-pin 80-pin 100-pin 0-00 --00 0-00 --00 u-uu --uu
REFO1CON 64-pin 80-pin 100-pin 0-00 0-00 u-uu u-uu u-uu u-uu
REFO1CON1 64-pin 80-pin 100-pin ---- 0000 ---- uuuu ---- uuuu
REFO1CON2 64-pin 80-pin 100-pin 0000 0000 uuuu uuuu uuuu uuuu
REFO1CON3 64-pin 80-pin 100-pin -000 0000 -uuu uuuu -uuu uuuu
REFO2CON 64-pin 80-pin 100-pin 0-00 0-00 u-uu u-uu u-uu u-uu
REFO2CON1 64-pin 80-pin 100-pin ---- 0000 ---- uuuu ---- uuuu
REFO2CON2 64-pin 80-pin 100-pin 0000 0000 uuuu uuuu uuuu uuuu
REFO2CON3 64-pin 80-pin 100-pin -000 0000 -uuu uuuu -uuu uuuu
LCDPS 64-pin 80-pin 100-pin 0000 0000 uuuu uuuu uuuu uuuu
LCDREG 64-pin 80-pin 100-pin 0000 0000 uuuu uuuu uuuu uuuu
VLCDCON 64-pin 80-pin 100-pin 0-11 1100 u-uu uuuu u-uu uuuu
LCDREFH 64-pin 80-pin 100-pin 0-00 0000 u-uu uuuu u-uu uuuu
TABLE 5-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out
Reset
MCLR
Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via
WDT or Interrupt
Legend: u = unchanged; x = unknown; - = unimplemented bit, read as ‘0’; q = value depends on condition.
Shaded cells indicate that conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-2 for Reset value for specific condition.
5: Bits 7,6 are unimplemented on 64 and 80-pin devices.
6: If the V
BAT is always powered, the DSGPx register values will remain unchanged after the first POR.