PIC18F97J94 FAMILY 8-Bit LCD Flash Microcontroller with USB and XLP Technology Extreme Low-Power Features: Peripheral Features (continued): • Multiple Power Management Options for Extreme Power Reduction: - VBAT allows for lowest power consumption on back-up battery (with or without RTCC) - Deep Sleep allows near total power-down with the ability to wake-up on external triggers - Sleep and Idle modes selectively shut down peripherals and/or core for substantial power reduction and fast wake-up • Alternate
PIC18F97J94 FAMILY Flash Program (bytes) Data SRAM (bytes) Timers 8-Bit/16-Bit USART w/IrDA® SPI w/ DMA Comparators CCP/ECCP I2C™ 10/12-Bit A/D (ch) CTMU LCD (pixels) USB Deep Sleep w/VBAT PPS (Lite) Remappable Peripherals Pins Memory PIC18F97J94 100 128K 4K 4 4 2 3 Y 2 24 Y 480 Y Y Lite PIC18F87J94 80 128K 4K 4 4 2 3 Y 2 24 Y 352 Y Y Lite PIC18F67J94 64 128K 4K 4 4 2 3 Y 2 16 Y 224 Y Y Lite PIC18F96J99 100 96K 4K 4 4 2 3 Y 2 24 Y
PIC18F97J94 FAMILY LCDBIAS3/RP30/CS/RE2 COM0/RP33/REFO1/RE3 COM1/RP32/RE4 COM2/RP37/RE5 COM3/RP34/RE6 LCDBIAS0/RP31/RE7 SEG0/RP20/PSP0/RD0 VDD VSS SEG1/RP21/PSP1/RD1 SEG2/RP22/PSP2/RD2 SEG3/RP23/PSP3/RD3 SEG4/RP24/PSP4/RD4 SEG5/SDA2/RP25/PSP5/RD5 SEG6/SCL2/RP26/PSP6/RD6 SEG7/RP27/REFO2/PSP7/RD7 Pin Diagrams 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 64-Pin TQFP, QFN LCDBIAS2/RP29/WR/RE1 LCDBIAS1/RP28/RD/RE0 COM4/SEG28/AN8/RP46/RG0 COM5/SEG29/AN19/RP39/RG1 COM6/SEG30/AN18/C3INA/RP42/RG2 COM7/SEG31/
PIC18F97J94 FAMILY A17/SEG46/AN22/RH1 A16/SEG47/AN23/RH0 AD10/LCDBIAS3/RP30/CS/RE2 AD11/COM0/RP33/REFO1/RE3 AD12/COM1/RP32/RE4 AD13/COM2/RP37/RE5 AD14/COM3/RP34/RE6 AD15/LCDBIAS0/RP31/RE7 AD0/SEG0/RP20/PSP0/RD0 VDD VSS AD1/SEG1/RP21/PSP1/RD1 AD2/SEG2/RP22/PSP2/RD2 AD3/SEG3/RP23/PSP3/RD3 AD4/SEG4/RP24/PSP4/RD4 AD5/SEG5/SDA2/RP25/PSP5/RD5 AD6/SEG6/SCL2/RP26/PSP6/RD6 AD7/SEG7/RP27/REFO2/PSP7/RD7 ALE/SEG32/RJ0 OE/SEG33/RJ1 Pin Diagrams (continued) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PIC18F97J94 FAMILY A17/SEG46/AN22/RH1 A16/SEG47/AN23/RH0 AD10/LCDBIAS3/RP30/CS/RE2 AD11/COM0/RP33/REFO1/RE3 RG7 AD12/COM1/RP32/RE4 AD13/COM2/RP37/RE5 AD14/COM3/RP34/RE6 AD15/LCDBIAS0/RP31/RE7 SEG48/RL0 AD0/SEG0/RP20/PSP0/RD0 RG6 VDD VSS AD1/SEG1/RP21/PSP1/RD1 SEG63/RK7 AD2/SEG2/RP22/PSP2/RD2 AD3/SEG3/RP23/PSP3/RD3 AD4/SEG4/RP24/PSP4/RD4 AD5/SEG5/SDA2/RP25/PSP5/RD5 SEG62/RK6 AD6/SEG6/SCL2/RP26/PSP6/RD6 AD7/SEG7/RP27/REFO2/PSP7/RD7 ALE/SEG32/RJ0 OE/SEG33/RJ1 Pin Diagrams (continued) 100 99 98 97 96 95 94 9
PIC18F97J94 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers ................................................................................................... 31 3.0 Oscillator Configurations ....................................................................................
PIC18F97J94 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
PIC18F97J94 FAMILY NOTES: DS30575A-page 8 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • • • • • • PIC18F97J94 PIC18F87J94 PIC18F67J94 PIC18F96J99 PIC18F86J99 PIC18F66J99 • • • • • • PIC18F96J94 PIC18F86J94 PIC18F66J94 PIC18F95J94 PIC18F85J94 PIC18F65J94 This family introduces a new line of low-voltage LCD microcontrollers with Universal Serial Bus (USB).
PIC18F97J94 FAMILY 1.1.3 MEMORY OPTIONS The PIC18F97J94 family provides ample room for application code, from 32 Kbytes to 128 Kbytes of code space. The Flash cells for program memory are rated to last up to 20,000 erase/write cycles. Data retention without refresh is conservatively estimated to be greater than 10 years. The Flash program memory is readable and writable.
PIC18F97J94 FAMILY 1.3 Other Special Features • Communications: The PIC18F97J94 family incorporates a range of serial communication peripherals, including USB, four Enhanced Addressable USARTs with IrDA, and two Master Synchronous Serial Port MSSP modules capable of both SPI and I2C™ (Master and Slave) modes of operation. • CCP Modules: PIC18F97J94 family devices incorporate up to seven Capture/Compare/PWM (CCP) modules.
PIC18F97J94 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE 64-PIN DEVICES Features PIC18F65J94 PIC18F66J94 32K 64K 96K 128K Operating Frequency Program Memory (Bytes) Program Memory (Instructions) PIC18F66J99 PIC18F67J94 DC – 64 MHz 16,384 32,768 49,152 65,536 Data Memory (Bytes) 4K 4K 4K 4K Interrupt Sources 42 48 I/O Ports Ports A, B, C, D, E, F, G Parallel Communications Parallel Slave Port (PSP) Timers 8 Comparators 3 LCD 224 pixels CTMU Yes RTCC Yes Enhanced Capture/Comp
PIC18F97J94 FAMILY TABLE 1-3: DEVICE FEATURES FOR THE 100-PIN DEVICES Features PIC18F95J94 PIC18F96J94 32 K 64K Operating Frequency Program Memory (Bytes) Program Memory (Instructions) PIC18F96J99 PIC18F97J94 DC – 64 MHz 96K 128K (Up to 2 Mbytes with Extended Memory) 16,384 32,768 49,152 65,536 Data Memory (Bytes) 4K 4K 4K 4K Interrupt Sources 42 I/O Ports Parallel Communications 48 Ports A, B, C, D, E, F, G, H, J, K, L Parallel Slave Port (PSP) Timers 8 Comparators 3 LCD CTMU RT
PIC18F97J94 FAMILY FIGURE 1-1: 64-PIN DEVICE BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 20 Address Latch PCU PCH PCL Program Counter 12 Data Address<12> 31-Level Stack 4 BSR Address Latch STKPTR Program Memory RB<7:0>(1) 12 PORTC RC<7:0>(1) inc/dec logic Table Latch Instruction Bus <16> PORTB 4 Access Bank 12 FSR0 FSR1 FSR2 Data Latch 8 RA<7:0>(1,2) Data Memory (4 Kbytes) PCLATU PCLATH 21 PORTA Data Latch 8 8 inc/dec logic Address Decode ROM Latch PORTD RD<7:0>(1) IR OSC2/C
PIC18F97J94 FAMILY FIGURE 1-2: 80-PIN DEVICE BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 8 8 inc/dec logic 20 Address Latch PCU PCH PCL Program Counter 31-Level Stack 4 BSR System Bus Interface STKPTR FSR0 FSR1 FSR2 Table Latch RD<7:0>(1) Address Decode Instruction Bus <16> PORTE RE<7:0>(1) IR AD<15:0>, A<19:16> (Multiplexed with PORTD, PORTE and PORTH) Instruction Decode and Control Timing Generation Power-up Timer INTRC Oscillator 8 MHz Oscillator Oscillator Start-up Timer Watchdog
PIC18F97J94 FAMILY FIGURE 1-3: 100-PIN DEVICE BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 8 8 inc/dec logic 20 PORTB 12 Data Address<12> 31-Level Stack 4 BSR Address Latch STKPTR 12 RB<7:0>(1) 4 Access Bank FSR0 FSR1 FSR2 Data Latch 8 RA<7:0>(1,2) Address Latch PCU PCH PCL Program Counter Program Memory PORTA Data Memory (4 Kbytes) PCLATU PCLATH 21 System Bus Interface Data Latch USB PORTC RC<7:0>(1) 12 PORTD inc/dec logic Table Latch RD<7:0>(1) Address Decode ROM Latch Inst
PIC18F97J94 FAMILY TABLE 1-4: PIC18F97J94 PINOUT I/O DESCRIPTIONS Pin Name Pin Number Pin 100 80 64 Type MCLR 11 9 7 OSC1/CLKI/RP10/RA7 61 49 39 I OSC1 CLKI I I RP10 RA7 I/O I/O OSC2/CLKO/RP6/RA6 62 50 40 OSC2 O CLKO O RP6 RA6 I/O I/O Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power I2C = I2C™/SMBus 2012 Microchip Technology Inc. Buffer Type ST Description Master Clear (input) or programming voltage (input).
PIC18F97J94 FAMILY TABLE 1-4: PIC18F97J94 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name SEG19/AN0/AN1-/RP0/RA0 Pin Number Pin 100 80 64 Type 37 36 34 33 43 SEG15 AN4 LVDIN C1INA C2INA C3INA RP5 RA5 Legend: 42 O I I/O I/O Analog Analog ST/DIG ST/DIG SEG18 output for LCD. Analog Input 1. Remappable Peripheral Pin 1 input/output. General purpose I/O pin. O I I I/O I/O Analog Analog Analog ST/DIG ST/DIG SEG21 output for LCD. A/D reference voltage (low) input. Analog Input 2.
PIC18F97J94 FAMILY TABLE 1-4: PIC18F97J94 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name VLCAP1/RP8/CTED13/INT0/RB0 Pin Number Pin 100 80 64 Type 73 72 70 69 68 67 65 PGD CTED6 RB7 Legend: 58 O I/O I I/O Analog ST/DIG ST ST/DIG SEG9 output for LCD. Remappable Peripheral Pin 14 input/output. CTMU Edge 1 input. General purpose I/O pin. O I/O I I/O Analog ST/DIG ST ST/DIG SEG10 output for LCD. Remappable Peripheral Pin 7 input/output. CTMU Edge 2 input. General purpose I/O pin.
PIC18F97J94 FAMILY TABLE 1-4: PIC18F97J94 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name SOSCO/SCLKI/PWRLCLK/RC0 Pin Number Pin 100 80 64 Type 45 Buffer Type Description 36 30 SOSCO SCLKI PWRLCLK O I I RC0 I/O SOSC oscillator output. Digital SOSC input. SOSC input at 50 Hz or 60 Hz only (RTCCLKSEL<1:0> = 11 or 10). ST/DIG General purpose I/O pin. I I/O Analog Timer1 oscillator input. ST/DIG General purpose I/O pin. O I I/O I I/O Analog Analog ST/DIG ST ST/DIG SEG13 output for LCD.
PIC18F97J94 FAMILY TABLE 1-4: PIC18F97J94 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name AD0/SEG0/RP20/PSP0/RD0 Pin Number Pin 100 80 64 Type 90 86 84 83 82 81 79 AD7 SEG7 RP27 REFO2 PSP7 RD7 Legend: 78 External Memory Address/Data 1. SEG1 output for LCD. Remappable Peripheral Pin 21 input/output. Parallel Slave Port data. General purpose I/O pin. I/O O I/O I/O I/O TTL/DIG Analog ST/DIG ST/DIG ST/DIG External Memory Address/Data 2. SEG2 output for LCD.
PIC18F97J94 FAMILY TABLE 1-4: PIC18F97J94 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name AD8/LCDBIAS1/RP28/RD/RE0 Pin Number Pin 100 80 64 Type 4 4 3 3 98 97 95 94 93 AD15 LCDBIAS0 RP31 RE7 Legend: 92 External Memory Address/Data 9. BIAS2 input for LCD. Remappable Peripheral Pin 29 input/output. Parallel Slave Port write strobe. General purpose I/O pin. I/O I I/O I I/O TTL/DIG Analog ST/DIG TTL ST/DIG External Memory Address/Data 10. BIAS3 input for LCD.
PIC18F97J94 FAMILY TABLE 1-4: PIC18F97J94 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name SEG20/AN7/CTMUI/C2INB/RP36/ RF2 Pin Number Pin 100 80 64 Type 23 22 20 19 18 SEG25 AN5 RP38 RF7 Legend: 17 I/O I — ST USB bus minus line input/output. General purpose input pin. I/O I — ST USB bus plus line input/output. General purpose input pin. O O I I I/O I/O Analog Analog Analog Analog ST/DIG ST/DIG SEG23 output for LCD. Comparator reference voltage output. Analog Input 10. Comparator 1 Input B.
PIC18F97J94 FAMILY TABLE 1-4: PIC18F97J94 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name COM4/SEG28/AN8/RP46/RG0 Pin Number Pin 100 80 64 Type 6 5 O O I I/O I/O Analog Analog Analog ST/DIG ST/DIG COM4 output for LCD. SEG28 output for LCD. Analog Input 8. Remappable Peripheral Pin 46 input/output. General purpose I/O pin. O O I I/O I/O Analog Analog Analog ST/DIG ST/DIG COM5 output for LCD. SEG29 output for LCD. Analog Input 19. Remappable Peripheral Pin 39 input/output. General purpose I/O pin.
PIC18F97J94 FAMILY TABLE 1-4: PIC18F97J94 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name A16/SEG47/AN23/RH0 Pin Number Pin 100 80 64 Type 99 1 2 27 26 25 SEG43 AN15 RH7 Legend: External Memory Address 17. SEG46 output for LCD. Analog Input 22. General purpose I/O pin. O O I I/O DIG Analog Analog ST/DIG External Memory Address 18. SEG45 output for LCD. Analog Input 21. General purpose I/O pin. O O I I/O DIG Analog Analog ST/DIG External Memory Address 19. SEG44 output for LCD. Analog Input 20.
PIC18F97J94 FAMILY TABLE 1-4: PIC18F97J94 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name ALE/SEG32/RJ0 Pin Number Pin 100 80 64 Type 77 76 75 74 49 50 51 UB SEG36 RJ7 Legend: 52 DIG External memory write low control. Analog SEG34 output for LCD. ST/DIG General purpose I/O pin. O O I/O DIG External memory write high control. Analog SEG35 output for LCD. ST/DIG General purpose I/O pin. O O I/O DIG External Memory Byte Address 0 control Analog SEG39 output for LCD.
PIC18F97J94 FAMILY TABLE 1-4: PIC18F97J94 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name SEG56/RK0 Pin Number Pin 100 80 64 Type SEG63 RK7 Legend: Analog SEG58 output for LCD. ST/DIG General purpose I/O pin. O I/O Analog SEG59 output for LCD. ST/DIG General purpose I/O pin. O I/O Analog SEG60 output for LCD. ST/DIG General purpose I/O pin. O I/O Analog SEG61 output for LCD. ST/DIG General purpose I/O pin. O I/O Analog SEG62 output for LCD. ST/DIG General purpose I/O pin.
PIC18F97J94 FAMILY TABLE 1-4: PIC18F97J94 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name SEG48/RL0 Pin Number Pin 100 80 64 Type Description 91 SEG48 RL0 SEG49/RL1 O I/O Analog SEG48 output for LCD. ST/DIG General purpose I/O pin. O I/O Analog SEG49 output for LCD. ST/DIG General purpose I/O pin. O I/O Analog SEG50 output for LCD. ST/DIG General purpose I/O pin. O I/O Analog SEG51 output for LCD. ST/DIG General purpose I/O pin. O I/O Analog SEG52 output for LCD.
PIC18F97J94 FAMILY TABLE 1-4: PIC18F97J94 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin 100 80 64 Type Buffer Type Description VDD1 VDD2 VDD3 VDD4 5 40 59 88 32 26 48 38 71 57 P — Positive supply for logic and I/O pins. VSS1 VSS2 VSS3 VSS4 Vss5 14 35 39 64 87 11 9 31 25 51 41 70 56 P — Ground reference for logic and I/O pins. AVDD 31 25 19 P — Positive supply for analog modules. AVSS 32 26 20 P — Ground reference for analog modules.
PIC18F97J94 FAMILY NOTES: DS30575A-page 30 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.
PIC18F97J94 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.
PIC18F97J94 FAMILY 2.4 Core Voltage Regulator (VCAP/VDDCORE) FIGURE 2-3: A low-ESR (< 5Ω) capacitor is required on the VCAP pin to stabilize the output voltage of the on-chip voltage regulator. The VCAP pin must not be connected to VDD and must use a capacitor of 10 μF connected to ground. The type can be ceramic or tantalum. Suitable examples of capacitors are shown in Table 2-1. Capacitors with equivalent specification can be used. FREQUENCY vs.
PIC18F97J94 FAMILY CONSIDERATIONS FOR CERAMIC CAPACITORS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. Ceramic capacitors are suitable for use with the VDDCORE voltage regulator of this microcontroller.
PIC18F97J94 FAMILY 2.6 External Oscillator Pins FIGURE 2-5: Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 3.0 “Oscillator Configurations” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins.
PIC18F97J94 FAMILY NOTES: DS30575A-page 36 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 3.0 OSCILLATOR CONFIGURATIONS • Software-controllable switching between various clock sources • Software-controllable postscaler for selective clocking of CPU for system power savings • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown • A separate and independently configurable system clock output for synchronizing external hardware This section describes the PIC18F oscillator system and its operation.
PIC18F97J94 FAMILY 3.1 CPU Clocking Scheme The system clock source can be provided by one of four sources: • Primary Oscillator (POSC) on the OSC1 and OSC2 pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins • Fast Internal RC (FRC) Oscillator • Low-Power Internal RC (LPRC) Oscillator FIGURE 3-2: The Primary Oscillator and FRC sources have the option of using the internal USB PLL block, which generates both the USB module clock and a separate system clock from the 96 MHz PLL.
PIC18F97J94 FAMILY 3.2 Oscillator Configuration The oscillator source (and operating mode) that is used at a device Power-on Reset (POR) event is selected using Configuration bit settings. The Oscillator Configuration bit settings are in the Configuration registers located in the program memory (refer to Section 28.1 “Configuration Bits” for more information).
PIC18F97J94 FAMILY 3.2.1 CLOCK SWITCHING MODE CONFIGURATION BITS The FSCMx Configuration bits (CONFIG3L<5:4>) are used to jointly configure device clock switching and the Fail-Safe Clock Monitor (FSCM). Clock switching is enabled only when FSCM1 is programmed (‘0’). The FSCM is enabled only when FSCM<1:0> are both programmed (‘00’). 3.2.
PIC18F97J94 FAMILY REGISTER 3-1: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R-x R-x R-x U-0 R/W-x R/W-x R/W-x IDLEN COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 IDLEN: Idle Enable bit 1 = SLEEP instruction invokes Idle mode 0 = SLEEP instruction invokes Sleep mode bit 6-4 COSC<2:0>: Current Oscillator Selection bits (read-only) 000 = Fast
PIC18F97J94 FAMILY REGISTER 3-2: OSCCON2: OSCILLATOR CONTROL REGISTER 2 R/W-0 R/W-0 R-0 U-0 R/C-0 R/W-0 R/W-0 U-0 CLKLOCK(2) IOLOCK(1) LOCK — CF POSCEN SOSCGO — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CLKLOCK: Clock Lock Enabled bit(2) 1 = Clock and PLL selection are locked and may not be modified 0 = Clock and PLL selection are not
PIC18F97J94 FAMILY 3.3.2 OSCCON3 – CLOCK DIVIDER REGISTER (IRCF<2:0> BITS) This option is described in more detail in Section 3.10.2 “FRC Postscaler Mode (FRCDIV)” and Section 3.10.3 “FRC Oscillator with PLL Mode (FRCPLL)”. The IRCFx bits (OSCCON3<2:0>) select the postscaler option for the FRC Oscillator output, allowing users to choose a lower clock frequency than the nominal 8 MHz.
PIC18F97J94 FAMILY 3.3.3 OSCILLATOR TUNING REGISTER (OSCTUNE) The FRC Oscillator Tuning register (Register 3-5) allows the user to fine-tune the FRC Oscillator. Refer to the data sheet of the specific device for further information regarding the FRC Oscillator tuning. REGISTER 3-5: The tuning response of the FRC Oscillator may not be monotonic or linear; the next closest frequency may be offset by a number of steps.
PIC18F97J94 FAMILY 3.4 Reference Clock Output Control Module The PIC18F97J94 family has two Reference Clock Output (REFO) modules. Each of the Reference Clock Output modules provides the user with the ability to send out a programmed output clock onto the REFO1or REFO2 pins. 3.4.1 REFERENCE CLOCK SOURCE 3.4.3 OPERATION IN SLEEP MODE If any clock source, other than the peripheral clock, is used as a base reference (i.e.
PIC18F97J94 FAMILY REGISTER 3-6: R/W-0 REFOxCON: REFERENCE CLOCK OUTPUT CONTROL REGISTER U-0 ON — R/W-0 SIDL R/W-0 OE R/W-0 (1) RSLP U-0 HC/R/W-0 HS/HC/R-0 — DIVSW_EN ACTIVE bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at all Resets ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ON: Reference Clock Output Enable bit 1 = Reference clock module is enabled 0 =
PIC18F97J94 FAMILY REGISTER 3-7: REFOxCON1: REFERENCE CLOCK OUTPUT CONTROL REGISTER 1 U-0 U-0 U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) — — — — ROSEL3 ROSEL2 ROSEL1 ROSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at all Resets ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ (Reserved for additional ROSEL bits.
PIC18F97J94 FAMILY REGISTER 3-8: REFOxCON2: REFERENCE CLOCK OUTPUT CONTROL REGISTER 2 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) R/W -0(1) R/W -0(1) RODIV7 RODIV6 RODIV5 RODIV4 RODIV3 RODIV2 RODIV1 RODIV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at all Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: x = Bit is unknown RODIV<7:0>: Reference Clock Output Divider bits(1) Reserved for expansion of ROD
PIC18F97J94 FAMILY 3.5 Primary Oscillator (POSC) input or an external crystal. Further details of the Primary Oscillator operating modes are described in subsequent sections. The Primary Oscillator has up to 6 operating modes, summarized in Table 3-2. The Primary Oscillator is available on the OSC1 and OSC2 pins of the PIC18F family.
PIC18F97J94 FAMILY 3.5.1 3.6 SELECTING A PRIMARY OSCILLATOR MODE Crystal Oscillators and Ceramic Resonators The main difference between the MS and HS modes is the gain of the internal inverter of the oscillator circuit, which allows the different frequency ranges. The MS mode is a medium power, medium frequency mode. HS mode provides the highest oscillator frequencies with a crystal. OSC2 provides crystal feedback in both HS and MS Oscillator modes.
PIC18F97J94 FAMILY 3.6.2 PRIMARY OSCILLATOR START-UP FROM SLEEP MODE The most difficult time for the oscillator to start-up is when waking up from Sleep mode. This is because the load capacitors have both partially charged to some quiescent value and phase differential at wake-up is minimal. Thus, more time is required to achieve stable oscillation. Also remember that low voltage, high temperatures and the lower frequency clock modes also impose limitations on loop gain, which in turn, affects start-up.
PIC18F97J94 FAMILY loop gain, such that if the circuit functions at these extremes, the designer can be more assured of proper operation at other temperatures and supply voltage combinations. The output sine wave should not be clipped in the highest gain environment (highest VDD and lowest temperature) and the sine output amplitude should be large enough in the lowest gain environment (lowest VDD and highest temperature) to cover the logic input requirements of the clock, as listed in the device data sheet.
PIC18F97J94 FAMILY PLL96MHZ submodule runs at 96 MHz and requires an input clock between 4 MHz and 48 MHz (a multiple of 4 MHz). These are selected through the PLLDIV<3:0> bits. FIGURE 3-7: BASIC OSCILLATOR BLOCK DIAGRAM FRCDIV FRC Oscillator (FRC) Divide by N OSCMUX PLL Module (PLLM, PLL96MHZ) Primary Oscillator (POSC) 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 3.8.1 OSCILLATOR MODES AND USB OPERATION Because of the timing requirements imposed by USB, an internal clock of 48 MHz is required at all times while the USB module is enabled and not in a suspended operating state. A method is provided to internally generate both the USB and system clocks from a single oscillator source. PIC18F97J94 family devices use the same clock structure as most other PIC18 devices, but include a two-branch PLL system to generate the two clock signals.
PIC18F97J94 FAMILY TABLE 3-3: SYSTEM CLOCK OPTIONS DURING USB OPERATION MCU Clock Division (CPDIV<1:0>) System Clock Frequency (Instruction Rate in MIPS) None (00) 64 MHz (16) 2 (01) 32 MHz (8) 4 (10) 4 MHz (4) (1) 8 (11) 2 MHz (1) Note 1: These options are not compatible with USB operation. They may be used whenever the PLL branch is selected and the USB module is disabled.
PIC18F97J94 FAMILY 3.9.2 3.9.2.1 SECONDARY OSCILLATOR OPERATION Continuous Operation The SOSC is always running when any of the SOSCEN bits are set. Leaving the oscillator running at all times allows a fast switch to the 32 kHz system clock for lower power operation. Returning to the faster main oscillator still requires an oscillator start-up time if it is a crystal-type source.
PIC18F97J94 FAMILY 3.11 Internal Low-Power RC Oscillator (LPRC) The LPRC Oscillator is separate from the FRC and oscillates at a nominal frequency of 31 kHz. LPRC is the clock source for the Power-up Timer (PWRT), Watchdog Timer (WDT) and FSCM circuits. It may also be used to provide a low-frequency clock source option for the device, in those applications where power consumption is critical and timing accuracy is not required. 3.11.
PIC18F97J94 FAMILY 3.13.1 ENABLING CLOCK SWITCHING 2. To enable clock switching, the FCKSM1 Configuration bit must be programmed to ‘0’. If the FCKSM1 Configuration bit is unprogrammed (‘1’), the clock switching function and Fail-Safe Clock Monitor function are disabled; this is the default setting. The NOSCx control bits (OSCCON<2:0>) do not control the clock selection when clock switching is disabled.
PIC18F97J94 FAMILY A recommended code sequence for a clock switch includes the following: 1. 2. 3. 4. 5. 6. Disable interrupts during the OSCCON register unlock and write sequence. Clear the CLKLOCK bit (OSCCON2<7>) to enable writes to the NOSCx bits (OSCCON<2:0>). Write new oscillator source to NOSCx control bits. Continue to execute code that is not clock-sensitive (optional).
PIC18F97J94 FAMILY Note 1: When the ACT module is enabled, the OSCTUNE register is only updated by the module. Writes to the OSCTUNE register by the user are inhibited, but reading the register is permitted. 2: After disabling the ACT module, the user should wait three instructions before writing to the OSCTUNE register.
PIC18F97J94 FAMILY REGISTER 3-10: ACTCON: ACTIVE CLOCK TUNING (ACT) CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 ACTEN — ACTSIDL ACTSRC(1) R-0 R/W-0 ACTLOCK ACTLOCKPOL R-0 R/W-0 ACTORS ACTORSPOL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ACTEN: Active Clock Tuning Selection bit 1 = ACT module is enabled, updates to OSCTUNE are exclusive to the ACT module 0 = ACT
PIC18F97J94 FAMILY 3.13.4 ABANDONING A CLOCK SWITCH In the event the clock switch does not complete, it can be abandoned by setting the NOSCx bits to their previous values. This abandons the clock switch process, stops and resets the OST (if applicable), and stops the PLL (if applicable). A clock switch procedure can be aborted at any time. A clock switch that is already in progress can also be aborted by performing a second clock switch. 3.13.
PIC18F97J94 FAMILY 3.15.3 CLOCK SYNCHRONIZATION The Reference Clock Output is enabled only once (ON = 1). Note that the source of the clock and the divider values should be chosen prior to the bit being set to avoid glitches on the REFO output. Once the ON bit is set, its value is synchronized to the reference clock domain to enable the output. This ensures that no glitches will be seen on the output.
PIC18F97J94 FAMILY NOTES: DS30575A-page 64 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 4.0 POWER-MANAGED MODES All PIC18F97J94 family devices offer a number of built-in strategies for reducing power consumption. These strategies can be particularly useful in applications, which are both power-constrained (such as battery operation), yet require periods of full-power operation for timing-sensitive routines (such as serial communications).
SUMMARY OF OPERATING MODES FOR PIC18F97J94 FAMILY DEVICES WITH VBAT POWER-SAVING FEATURES Exit Conditions Active Systems INT0 Only All POR MCLR RTCC Alarm (DS)WDT(3) VDD Restore Y Y Y Y N/A N/A N/A N/A N/A N/A N/A N/A N/A Y Y Y Y Y Y Y Y Y Y Y N/A Next Instruction Instruction N N(4) Y Y Y Y Y Y Y Y Y Y N/A Next Instruction Instruction + RETEN bit N (4) Y Y Y Y Y Y Y Y Y Y N/A Retention Deep Sleep Instruction + DSEN bit + RETEN bit N N Y Y
PIC18F97J94 FAMILY 4.2 Instruction-Based Power-Saving Modes PIC18F97J94 family devices have 3 instruction-based power-saving modes; two of these have additional features that allow for additional tailoring of power consumption. All three modes are entered through the execution of the SLEEP instruction. In descending order of power consumption, they are: • Idle Mode: The CPU is disabled, but the system clock source continues to operate. Peripherals continue to operate, but can optionally be disabled.
PIC18F97J94 FAMILY 4.2.3 IDLE MODE When the device enters Idle mode, the following events occur: • The CPU will stop executing instructions. • The WDT is automatically cleared. • The system clock source will remain active and the peripheral modules, by default, will continue to operate normally from the system clock source. Peripherals can optionally be shut down in Idle mode using their ‘Stop in Idle’ control bit. (See peripheral descriptions for further details.
PIC18F97J94 FAMILY 4.2.4.1 Retention Sleep Mode Retention Sleep mode allows for additional power savings over Sleep mode by maintaining key systems from the lower power retention regulator. When the retention regulator is used, the normal on-chip voltage regulator (operating at 1.8V nominal) is turned off and will enable a low-power (1.2V typical) regulator. By using a lower voltage, a lower total power consumption is achieved.
PIC18F97J94 FAMILY TABLE 4-3: DELAY TIMES FOR EXITING FROM SLEEP MODE Clock Source Exit Delay Oscillator Delay Notes EC TPM — ECPLL TPM TLOCK 1, 3 1, 2 1 MS, HS TPM TOST MSPLL, HSPLL TPM TOST + TLOCK SOSC (Off during Sleep) TPM TOST (On during Sleep) TPM — TPM TFRC 1, 4 (Off during Sleep) TPM TLPRC 1, 4 (On during Sleep) TPM — TPM TLOCK FRC, FRCDIV LPRC FRCPLL Note 1: 2: 3: 4: 1, 2, 3 1, 2 1 1 1, 3 TPM = Start-up delay for program memory stabilization.
PIC18F97J94 FAMILY 4.4 Deep Sleep Modes The Deep Sleep modes puts the device into its lowest power consumption states without requiring the use of external switches to remove power from the device. There are two modes available: Deep Sleep mode and Retention Deep Sleep mode. During both Deep Sleep modes, the power to the microcontroller core is removed to reduce leakage current. Therefore, most peripherals and functions of the microcontroller become unavailable during Deep Sleep.
PIC18F97J94 FAMILY 4.4.5 SAVING CONTEXT DATA WITH THE DSGPRx REGISTERS As exiting Deep Sleep mode causes a POR, most Special Function Registers (SFRs) reset to their default POR values. In addition, because the core power is not supplied in Deep Sleep mode, information in data RAM may be lost when exiting this mode. Applications which require critical data to be saved prior to Deep Sleep may use the Deep Sleep General Purpose registers, DSGPR0, DSGPR1, DSGPR2 and DSGPR3.
PIC18F97J94 FAMILY 4.4.10 CONTROL BIT SUMMARY FOR SLEEP MODES Table 4-5 shows the settings for the bits relevant to Deep Sleep modes. TABLE 4-5: BIT SETTINGS FOR ALL DEEP SLEEP MODES Instruction-Based Mode DSEN (DSCONH<7>) Retention Deep Sleep Deep Sleep 4.4.
PIC18F97J94 FAMILY TABLE 4-7: DELAY TIMES FOR EXITING RETENTION DEEP SLEEP MODE Clock Source Exit Delay Oscillator Delay EC TRETR + TPM — ECPLL TRETR + TPM TLOCK 1, 2, 4, 6 MS, HS TRETR + TPM TOST 1, 2, 3, 6 MSPLL, HSPLL TRETR + TPM TOST + TLOCK Off during Sleep TRETR + TPM TOST On during Sleep TRETR + TPM — SOSC 4: 5: 6: 1, 2, 3, 4, 6 1, 2, 3, 6 1, 2, 6 TFRC 1, 2, 5, 6 Off during Sleep TRETR + TPM TLPRC 1, 2, 5, 6 On during Sleep TRETR + TPM — TRETR + TPM TLOCK TRETR
PIC18F97J94 FAMILY 4.5 VBAT Mode Entering VBAT mode requires that a power source, distinct from the main VDD power source, be available on VBAT and that VDD be completely removed from the VDD pin(s). Removing VDD can be either unintentional, as in a power failure, or as part of a deliberate power reduction strategy. VBAT mode is a hardware-based power mode that maintains only the most critical operations when a power loss occurs on VDD.
PIC18F97J94 FAMILY 4.5.1 WAKE-UP FROM VBAT MODES When VDD is restored to a device in VBAT mode, it automatically wakes. Wake-up occurs with a POR, after which the device starts executing code from the Reset vector. All SFRs, except the Deep Sleep semaphores and RTCC registers are reset to their POR values. If the RTCC was not configured to run during VBAT mode, it will remain disabled and RTCC will not run. Wake-up timing is similar to that for a normal POR.
PIC18F97J94 FAMILY REGISTER 4-1: DSCONL: DEEP SLEEP CONTROL REGISTER LOW U-0 U-0 U-0 U-0 U-0 R-0 R/W-0, HSC R/W-0, HS — — — — — r DSBOR(1) RELEASE(1) bit 7 bit 0 Legend: r = Reserved bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown HS = Hardware Settable bit bit 7-3 Unimplemented: Read as ‘0’ bit 2 Reserved: Maintained as ‘0’ bit 1 DSBOR:
PIC18F97J94 FAMILY DSWAKEL: DEEP SLEEP WAKE-UP SOURCE REGISTER LOW(1) REGISTER 4-3: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DSFLT BOR EXT DSWDT DSRTC MCLR ICD DSPOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DSFLT: Deep Sleep Fault Detect bit 1 = A Deep Sleep Fault was detected during Deep Sleep 0 = A Deep Sleep Fault was not detected during Deep S
PIC18F97J94 FAMILY 4.7 Selective Peripheral Power Control Sleep and Idle modes allow users to substantially reduce power consumption by slowing or stopping the CPU clock. Even so, peripheral modules still remain clocked, and thus, consume some amount of power. There may be cases where the application needs what these modes do not provide: the ability to allocate limited power resources to the CPU while eliminating power consumption from the peripherals.
PIC18F97J94 FAMILY REGISTER 4-5: PMD0: PERIPHERAL MODULE DISABLE REGISTER 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCP10MD CCP9MD CCP8MD CCP7MD CCP6MD CCP5MD CCP4MD ECCP3MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CCP10MD: CCP10 Module Disable bit 1 = The CCP10 module is disabled. All CCP10 registers are held in Reset and are not writable.
PIC18F97J94 FAMILY REGISTER 4-6: PMD1: PERIPHERAL MODULE DISABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCP2MD ECCP1MD UART4MD UART3MD UART2MD UART1MD SSP2MD SSP1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCP2MD: ECCP2 Module Disable bit 1 = The ECCP2 module is disabled. All ECCP2 registers are held in Reset and are not writable.
PIC18F97J94 FAMILY REGISTER 4-7: PMD2: PERIPHERAL MODULE DISABLE REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMR8MD TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR8MD: Timer8 Module Disable bit 1 = The Timer8 module is disabled. All Timer8 registers are held in Reset and are not writable.
PIC18F97J94 FAMILY REGISTER 4-8: PMD3: PERIPHERAL MODULE DISABLE REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXMMD CTMUMD ADCMD RTCCMD LCDMD PSPMD REFO1MD REFO2MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 x = Bit is unknown TXMMD: Modulator Output Module Disable bit 1 = The Modulator Output module is disabled.
PIC18F97J94 FAMILY REGISTER 4-9: PMD4: PERIPHERAL MODULE DISABLE REGISTER 4 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 CMP1MD CMP2MD CMP3MD USBMD IOCMD LVDMD — EMBMD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CMP1MD: CMP1 Module Disable bit 1 = The CMP1 module is disabled; all CMP1 registers are held in Reset and are not writable 0 = The CMP1 module is
PIC18F97J94 FAMILY 5.0 RESET The PIC18F97J94 family devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) Power-on Reset (POR) MCLR Reset Watchdog Timer (WDT) Reset Configuration Mismatch (CM) Brown-out Reset (BOR) RESET Instruction Stack Underflow/Overflow Reset This section discusses Resets generated by MCLR, POR and BOR, and covers the operation of the various start-up timers. For information on WDT Resets, see Section 28.2 “Watchdog Timer (WDT)”.
PIC18F97J94 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0(1) R/W-0 IPEN — CM RI TO PD POR BOR bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable Register bit 1 = Prioritized interrupts are enabled 0 = Prioritized interrupts are disabled bit 6 Unimplemented: Rea
PIC18F97J94 FAMILY REGISTER 5-2: R/W-0, HS RCON2: RESET CONTROL REGISTER 2 U-0 (1) EXTR — R/W-0 (2) SWDTEN U-0 U-0 U-0 U-0 U-0 — — — — — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 EXTR: External Reset (MCLR) Pin bit(1) 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred bit 6 Unimplemented: Read as ‘0’ bi
PIC18F97J94 FAMILY REGISTER 5-3: U-0 RCON3: RESET CONTROL REGISTER 3 U-0 — — U-0 — U-0 — R/C-0 R/C-0 (1) VDDBOR VDDPOR R/C-0 (1,2) (1,3) VBPOR R/W-0 VBAT bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 VDDBOR: VDD Brown-out Reset Flag bit(1) 1 = A VDD Brown-out Reset has occurred 0 = A VDD Brown-out Reset has not occurred bit
PIC18F97J94 FAMILY REGISTER 5-4: RCON4: RESET CONTROL REGISTER 4 U-0 U-0 U-0 R/W-0 U-0 R/C-0 U-0 R/W-0 — — — SRETEN(1) — DPSLP(2) — PMSLP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 SRETEN: Retention Regulator Voltage Sleep Disable bit(1) 1 = If RETEN (CONFIG7L<0>) = 0 and the regulator is enabled, the device goes into
PIC18F97J94 FAMILY 5.2 Power-on Reset (POR) The PIC18F97J94 family has two types of Power-on Resets: • POR • VBAT POR POR is the legacy PIC18J series Power-on Reset which monitors core power supply. The second, VBAT POR, monitors voltage on the VBAT pin. These POR circuits use the same technique to enable and monitor their respective power source for adequate voltage levels to ensure proper chip operation. There are two threshold voltages associated with them.
PIC18F97J94 FAMILY FIGURE 5-2: POR MODULE TIMING SEQUENCE FOR RISING VDD POR Circuit Threshold Voltage VDD VPOR Internal Power-on Reset Pulse Occurs and Begins POR Delay Time, TCSD POR TCSD POR Circuit is Initialized at VPOR System Clock is Started After TPWRT Delay Expires PWRT TPWRT System Clock is Released and Code Execution Begins SYSRST (Note 1) System Reset is Released After Clock is Stable Oscillator Delay INTERNAL RESET Time Note 1: Timer and interval are determined by the initial start-u
PIC18F97J94 FAMILY 5.2.1.1 Using the POR Circuit To take advantage of the POR circuit, tie the MCLR pin directly to VDD. This will eliminate external RC components usually needed to create a POR delay. A minimum rise time for VDD is required. Refer to the “Electrical Characteristics” section of the specific device data sheet for more information. Depending on the application, a resistor may be required between the MCLR pin and VDD.
PIC18F97J94 FAMILY 5.5 Configuration Mismatch Reset (CM) 5.6 The Configuration Mismatch (CM) Reset is designed to detect, and attempt to recover from, random memory corrupting events. These include Electrostatic Discharge (ESD) events, which can cause widespread, single bit changes throughout the device and result in catastrophic failure.
PIC18F97J94 FAMILY 5.6.1 BROWN-OUT RESET (BOR) Brown-out Reset is the legacy PIC18 “J” feature that monitors the core voltage, VDDCORE. Since the regulator on the PIC18F97J94 family is always enabled, this feature is always active. Its trip point is non-configurable. A Brown-out Reset will occur as the regulator output voltage drops below, approximately 1.6V. After proper operating voltage recovers, the Brown-out Reset condition is exited and execution begins after the Power-up Timer has expired.
PIC18F97J94 FAMILY 5.9 Device Reset Timers PIC18F97J94 family devices incorporate three separate on-chip timers that help regulate the Power-on Reset process. Their main function is to ensure that the device clock is stable before code is executed. These timers are: • Power-up Timer (PWRT) • Oscillator Start-up Timer (OST) • PLL Lock Time-out 5.9.1 POWER-UP TIMER (PWRT) The Power-up Timer (PWRT) of the PIC18F97J94 family devices is a counter which uses the INTOSC source as the clock input.
PIC18F97J94 FAMILY DPSLP EXTR RI TO PD IDLE CM BOR POR VDDBOR VDDPOR VBPOR(4,6) VBAT(4) RCONx BIT OPERATION ON VARIOUS RESETS AND WAKE-UPS PC TABLE 5-2: DSPOR:(4) Loss of VDDBAT 000000 0 0 0 0 1 0 0 1 1 1 1 1 0 VBAT:(4) Loss of VDD While VBAT is Established 000000 1 0 0 0 1 0 0 1 1 1 1 u 1 VDD POR: Loss of VDD 000000 0 0 0 0 1 0 0 1 1 1 1 u u VDD BOR: Brown-out of VDD 000000 u u 0 0 1 0 0 u u 1 u u u POR: Loss of VDDCORE 000000 0
PIC18F97J94 FAMILY TABLE 5-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices MCLR Resets, Power-on Reset, WDT Reset, Wake-up via Brown-out RESET Instruction, WDT or Interrupt Reset Stack Resets TOSU 64-pin 80-pin 100-pin ---0 0000 ---0 0000 ---0 uuuu(1) TOSH 64-pin 80-pin 100-pin 0000 0000 0000 0000 uuuu uuuu(1) TOSL 64-pin 80-pin 100-pin 0000 0000 0000 0000 uuuu uuuu(1) STKPTR 64-pin 80-pin 100-pin 00-0 0000 uu-0 0000 uu-u uuuu(1) PCLATU 64-pin 80-p
PIC18F97J94 FAMILY TABLE 5-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices MCLR Resets, Power-on Reset, WDT Reset, Wake-up via Brown-out RESET Instruction, WDT or Interrupt Reset Stack Resets POSTINC2 64-pin 80-pin 100-pin N/A N/A N/A POSTDEC2 64-pin 80-pin 100-pin N/A N/A N/A PREINC2 64-pin 80-pin 100-pin N/A N/A N/A PLUSW2 64-pin 80-pin 100-pin N/A N/A N/A FSR2H 64-pin 80-pin 100-pin ---- xxxx ---- uuuu ---- uuuu FSR2L 64-pin 8
PIC18F97J94 FAMILY TABLE 5-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices MCLR Resets, Power-on Reset, WDT Reset, Wake-up via Brown-out RESET Instruction, WDT or Interrupt Reset Stack Resets ECCP1AS 64-pin 80-pin 100-pin 0000 0000 0000 0000 uuuu uuuu ECCP1DEL 64-pin 80-pin 100-pin 0000 0000 uuuu uuuu uuuu uuuu CCPR1H 64-pin 80-pin 100-pin xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L 64-pin 80-pin 100-pin xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 64
PIC18F97J94 FAMILY TABLE 5-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices MCLR Resets, Power-on Reset, WDT Reset, Wake-up via Brown-out RESET Instruction, WDT or Interrupt Reset Stack Resets PSTR1CON 64-pin 80-pin 100-pin 00-0 0001 00-0 0001 uu-u uuuu OSCTUNE 64-pin 80-pin 100-pin --00 0000 --00 0000 --uu uuuu TRISJ 64-pin 80-pin 100-pin 1111 1111 1111 1111 uuuu uuuu TRISH 64-pin 80-pin 100-pin 1111 1111 1111 1111 uuuu uuuu TRISG(5) 6
PIC18F97J94 FAMILY TABLE 5-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices MCLR Resets, Power-on Reset, WDT Reset, Wake-up via Brown-out RESET Instruction, WDT or Interrupt Reset Stack Resets RCON4 64-pin 80-pin 100-pin 00-0 -0-0 00-u -0-u 00-u -0-u UFRML 64-pin 80-pin 100-pin xxxx xxxx xxxx xxxx uuuu uuuu UFRMH 64-pin 80-pin 100-pin ---- -xxx ---- -xxx ---- -uuu UIR 64-pin 80-pin 100-pin -000 0000 -000 0000 -uuu uuuu UEIR 64-pin 80-pin
PIC18F97J94 FAMILY TABLE 5-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices MCLR Resets, Power-on Reset, WDT Reset, Wake-up via Brown-out RESET Instruction, WDT or Interrupt Reset Stack Resets ALRMRPT 64-pin 80-pin 100-pin 0000 0000 uuuu uuuu uuuu uuuu ALRMVALH 64-pin 80-pin 100-pin xxxx xxxx uuuu uuuu uuuu uuuu ALRMVALL 64-pin 80-pin 100-pin xxxx xxxx uuuu uuuu uuuu uuuu RTCCON2 64-pin 80-pin 100-pin 0000 0000 uuuu uuuu uuuu uuuu IOCP
PIC18F97J94 FAMILY TABLE 5-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices MCLR Resets, Power-on Reset, WDT Reset, Wake-up via Brown-out RESET Instruction, WDT or Interrupt Reset Stack Resets SSP2CON3 64-pin 80-pin 100-pin 0000 0000 0000 0000 uuuu uuuu CM2CON 64-pin 80-pin 100-pin 0001 1111 0001 1111 uuuu uuuu CM3CON 64-pin 80-pin 100-pin 0001 1111 0001 1111 uuuu uuuu CCPTMRS0 64-pin 80-pin 100-pin 0000 0000 0000 0000 uuuu uuuu CCPTMRS1
PIC18F97J94 FAMILY TABLE 5-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices MCLR Resets, Power-on Reset, WDT Reset, Wake-up via Brown-out RESET Instruction, WDT or Interrupt Reset Stack Resets SSP2CON2 64-pin 80-pin 100-pin 0000 0000 0000 0000 uuuu uuuu SSP2MSK 64-pin 80-pin 100-pin 1111 1111 1111 1111 uuuu uuuu TMR5H 64-pin 80-pin 100-pin xxxx xxxx uuuu uuuu uuuu uuuu TMR5L 64-pin 80-pin 100-pin xxxx xxxx uuuu uuuu uuuu uuuu T5CON 64-p
PIC18F97J94 FAMILY TABLE 5-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices MCLR Resets, Power-on Reset, WDT Reset, Wake-up via Brown-out RESET Instruction, WDT or Interrupt Reset Stack Resets CTMUCON1 64-pin 80-pin 100-pin 0000 0000 0000 0000 uuuu uuuu CTMUCON2 64-pin 80-pin 100-pin 0000 00-- 0000 00-- uuuu uu-- CTMUCON3 64-pin 80-pin 100-pin 0000 0000 0000 0000 uuuu uuuu PMD0 64-pin 80-pin 100-pin 0000 0000 0000 0000 uuuu uuuu PMD1 64-p
PIC18F97J94 FAMILY TABLE 5-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices MCLR Resets, Power-on Reset, WDT Reset, Wake-up via Brown-out RESET Instruction, WDT or Interrupt Reset Stack Resets LCDREFL 64-pin 80-pin 100-pin 0000 -000 uuuu -uuu uuuu -uuu LCDSE7 64-pin 80-pin 100-pin 0000 0000 uuuu uuuu uuuu uuuu LCDSE6 64-pin 80-pin 100-pin 0000 0000 uuuu uuuu uuuu uuuu LCDSE5 64-pin 80-pin 100-pin 0000 0000 uuuu uuuu uuuu uuuu LCDSE4 64-
PIC18F97J94 FAMILY TABLE 5-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices MCLR Resets, Power-on Reset, WDT Reset, Wake-up via Brown-out RESET Instruction, WDT or Interrupt Reset Stack Resets LCDDATA39 64-pin 80-pin 100-pin 0000 0000 uuuu uuuu uuuu uuuu LCDDATA38 64-pin 80-pin 100-pin 0000 0000 uuuu uuuu uuuu uuuu LCDDATA37 64-pin 80-pin 100-pin 0000 0000 uuuu uuuu uuuu uuuu LCDDATA36 64-pin 80-pin 100-pin 0000 0000 uuuu uuuu uuuu uuuu LC
PIC18F97J94 FAMILY TABLE 5-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices MCLR Resets, Power-on Reset, WDT Reset, Wake-up via Brown-out RESET Instruction, WDT or Interrupt Reset Stack Resets LCDDATA6 64-pin 80-pin 100-pin 0000 0000 uuuu uuuu uuuu uuuu LCDDATA5 64-pin 80-pin 100-pin 0000 0000 uuuu uuuu uuuu uuuu LCDDATA4 64-pin 80-pin 100-pin 0000 0000 uuuu uuuu uuuu uuuu LCDDATA3 64-pin 80-pin 100-pin 0000 0000 uuuu uuuu uuuu uuuu LCDD
PIC18F97J94 FAMILY TABLE 5-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices MCLR Resets, Power-on Reset, WDT Reset, Wake-up via Brown-out RESET Instruction, WDT or Interrupt Reset Stack Resets ADCBUF22H 64-pin 80-pin 100-pin xxxx xxxx xxxx xxxx uuuu uuuu ADCBUF22L 64-pin 80-pin 100-pin xxxx xxxx xxxx xxxx uuuu uuuu ADCBUF21H 64-pin 80-pin 100-pin xxxx xxxx xxxx xxxx uuuu uuuu ADCBUF21L 64-pin 80-pin 100-pin xxxx xxxx xxxx xxxx uuuu uuuu AD
PIC18F97J94 FAMILY TABLE 5-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices MCLR Resets, Power-on Reset, WDT Reset, Wake-up via Brown-out RESET Instruction, WDT or Interrupt Reset Stack Resets ADCBUF6L 64-pin 80-pin 100-pin xxxx xxxx xxxx xxxx uuuu uuuu ADCBUF5H 64-pin 80-pin 100-pin xxxx xxxx xxxx xxxx uuuu uuuu ADCBUF5L 64-pin 80-pin 100-pin xxxx xxxx xxxx xxxx uuuu uuuu ADCBUF4H 64-pin 80-pin 100-pin xxxx xxxx xxxx xxxx uuuu uuuu ADCB
PIC18F97J94 FAMILY TABLE 5-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices MCLR Resets, Power-on Reset, WDT Reset, Wake-up via Brown-out RESET Instruction, WDT or Interrupt Reset Stack Resets RPINR14_15 64-pin 80-pin 100-pin 1111 1111 1111 1111 uuuu uuuu RPINR12_13 64-pin 80-pin 100-pin 1111 1111 1111 1111 uuuu uuuu RPINR10_11 64-pin 80-pin 100-pin 1111 1111 1111 1111 uuuu uuuu RPINR8_9 64-pin 80-pin 100-pin 1111 1111 1111 1111 uuuu uuuu
PIC18F97J94 FAMILY TABLE 5-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices MCLR Resets, Power-on Reset, WDT Reset, Wake-up via Brown-out RESET Instruction, WDT or Interrupt Reset Stack Resets UIE 64-pin 80-pin 100-pin -000 0000 -000 0000 -uuu uuuu UEIE 64-pin 80-pin 100-pin 0--0 0000 0--0 0000 u--u uuuu UEP0 64-pin 80-pin 100-pin ---0 0000 ---0 0000 ---u uuuu UEP1 64-pin 80-pin 100-pin ---0 0000 ---0 0000 ---u uuuu UEP2 64-pin 80-pin
PIC18F97J94 FAMILY 6.0 MEMORY ORGANIZATION As Harvard architecture devices, the data and program memories use separate busses. This enables concurrent access of the two memory spaces. Additional detailed information on the operation of the Flash program memory is provided in Section 7.0 “Flash Program Memory”.
PIC18F97J94 FAMILY 6.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit Program Counter that is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘0’s (a NOP instruction). The entire PIC18F97J94 family offers a range of on-chip Flash program memory sizes, from 32 Kbytes (up to 16,384 single-word instructions) to 128 Kbytes (65,536 single-word instructions).
PIC18F97J94 FAMILY 6.1.3 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits and is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU.
PIC18F97J94 FAMILY 6.1.4.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 6-1) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. On Reset, the Stack Pointer value will be zero.
PIC18F97J94 FAMILY 6.1.4.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit (CONFIG1L<5>). When STVREN is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device Reset. The STKFUL or STKUNF bits are cleared by user software or a Power-on Reset.
PIC18F97J94 FAMILY 6.2 PIC18 Instruction Cycle 6.2.1 6.2.2 An “Instruction Cycle” consists of four Q cycles, Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction (such as GOTO) causes the Program Counter to change, two cycles are required to complete the instruction.
PIC18F97J94 FAMILY 6.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as two or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). To maintain alignment with instruction boundaries, the PC increments in steps of two and the LSB will always read ‘0’ (see Section 6.1.3 “Program Counter”).
PIC18F97J94 FAMILY 6.3 Note: Data Memory Organization The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 6.6 “Data Memory and the Extended Instruction Set” for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4,096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each.
PIC18F97J94 FAMILY FIGURE 6-6: DATA MEMORY MAP FOR PIC18F97J94 FAMILY DEVICES BSR<3:0> Data Memory Map 00h = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 Bank 0 FFh 00h Bank 1 GPR 1FFh 200h FFh 00h Bank 2 GPR FFh 00h Bank 3 2FFh 300h GPR FFh 00h Bank 4 3FFh 400h 6FFh 700h GPR FFh 00h 7FFh 800h GPR Bank 9 8FFh 900h The BSR specifies the bank used by the instruction.
PIC18F97J94 FAMILY FIGURE 6-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) 7 0 0 0 0 0 0 0 Bank Select(2) 1 0 000h Data Memory Bank 0 100h Bank 1 200h 300h Bank 2 00h 7 FFh 00h 1 From Opcode(2) 1 1 1 1 1 0 1 1 FFh 00h FFh 00h Bank 3 through Bank 13 E00h Bank 14 F00h FFFh Note 1: 2: 6.3.2 Bank 15 FFh 00h FFh 00h FFh The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank.
PIC18F97J94 FAMILY 6.3.4 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy all of Bank 15 (F00h to FFFh), Bank 14 (E00h to EFFh) and part of Bank 13 (DFAh to DFFh). A list of these registers is given in Table 6-2. 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY TABLE 6-2: REGISTER FILE SUMMARY File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 — — — Top-of-Stack Upper Byte (TOS<20:16>) Bit 2 Bit 1 Bit 0 FFFh TOSU FFEh TOSH Top-of-Stack High Byte (TOS<15:8>) FFDh TOSL Top-of-Stack Low Byte (TOS<7:0>) FFCh STKPTR STKFUL STKUNF — STKPTR FFBh PCLATU — — — Holding Register for PC<20:16> FFAh PCLATH Holding Register for PC<15:8> FF9h PCL PC Low Byte (PC<7:0>) FF8h TBLPTRU FF7h TBLPTRH FF6h TBLPTRL Program Memory Tab
PIC18F97J94 FAMILY TABLE 6-2: File Name FCFh REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 TMR1H Timer1 Register High Byte FCEh TMR1L Timer1 Register Low Byte FCDh T1CON TMR1CS1 TMR1CS0 FCCh TMR2 Timer2 Register FCBh PR2 Timer2 Period Register FCAh T2CON — T2OUTPS3 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T1CKPS1 T1CKPS0 SOSCEN T1SYNC RD16 TMR1ON T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 FC9h SSP1BUF MSSP1 Receive Buffer/Transmit Register FC8h SSP1ADD MSSP1 Address
PIC18F97J94 FAMILY TABLE 6-2: REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STRA F9Ch PSTR1CON CMPL1 CMPL0 — STRSYNC STRD STRC STRB F9Bh OSCTUNE — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 F9Ah TRISJ TRISJ7 TRISJ6 TRISJ5 TRISJ4 TRISJ3 TRISJ2 TRISJ1 TRISJ0 F99h TRISH TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 F98h TRISG TRISG7 TRISG6 — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 F97h TRISF TRISF7 TRISF6 TR
PIC18F97J94 FAMILY TABLE 6-2: File Name REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DHEN F69h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN F68h SSP1MSK MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 F67h BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 IREN WUE ABDEN F66h OSCCON2 CLKLOCK IOLOCK LOCK — CF POSCEN SOSCGO — F65h OSCCON3 — — — — — IRCF2 IRCF1 IRCF0 F64h OSCCON4 CPDIV1 CPDIV0 PLLEN — — — — — F63h ACTCON
PIC18F97J94 FAMILY TABLE 6-2: REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F36h CCPTMRS0 C3TSEL1 C3TSEL0 C2TSEL2 C2TSEL1 C2TSEL0 C1TSEL2 C1TSEL1 C1TSEL0 F35h CCPTMRS1 C7TSEL1 C7TSEL0 — C6TSEL0 — C5TSEL0 C4TSEL1 C4TSEL0 F34h CCPTMRS2 — — — C10TSEL0 — C9TSEL0 C8TSEL1 C8TSEL0 F33h RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D F32h TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D F31h BAUDCON2 ABDOVF RC
PIC18F97J94 FAMILY TABLE 6-2: File Name REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 F03h SSP2BUF MSSP2 Receive Buffer/Transmit Register F02h SSP2ADD MSSP2 Address Register in I2C™ Slave Mode. MSSP1 Baud Rate Reload Register in I2C Master Mode.
PIC18F97J94 FAMILY TABLE 6-2: REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ECFh LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE09 SE08 ECEh LCDSE0 SE07 SE06 SE05 SE04 SE03 SE02 SE01 SE00 ECDh LCDDATA63 S63C7 S62C7 S61C7 S60C7 S59C7 S58C7 S57C7 S56C7 ECCh LCDDATA62 S55C7 S54C7 S53C7 S52C7 S51C7 S50C7 S49C7 S48C7 ECBh LCDDATA61 S47C7 S46C7 S45C7 S44C7 S43C7 S42C7 S41C7 S40C7 ECAh LCDDATA60 S39C7 S38C7 S37C7 S36C
PIC18F97J94 FAMILY TABLE 6-2: REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 E9Ch LCDDATA14 S55C1 S54C1 S53C1 S52C1 S51C1 S50C1 S49C1 S48C1 E9Bh LCDDATA13 S47C1 S46C1 S45C1 S44C1 S43C1 S42C1 S41C1 S40C1 E9Ah LCDDATA12 S39C1 S38C1 S37C1 S36C1 S35C1 S34C1 S33C1 S32C1 E99h LCDDATA11 S31C1 S30C1 S29C1 S28C1 S27C1 S26C1 S25C1 S24C1 E98h LCDDATA10 S23C1 S22C1 S21C1 S20C1 S19C1 S18C1 S17C1 S16C1 E97h LCDDATA9
PIC18F97J94 FAMILY TABLE 6-2: REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 E69h ADCBUF17H E68h ADCBUF17L A/D Result Register 17 Low Byte E67h ADCBUF16H A/D Result Register 16 High Byte Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 A/D Result Register 17 High Byte E66h ADCBUF16L A/D Result Register 16 Low Byte E65h ADCBUF15H A/D Result Register 15 High Byte E64h ADCBUF15L A/D Result Register 15 Low Byte E63h ADCBUF14H A/D Result Register 14 High Byte E62h ADCBUF14L A/D Resu
PIC18F97J94 FAMILY TABLE 6-2: File Name REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 E36h RPINR24_25 IOC7R<3:0> IOC6R<3:0> E35h RPINR22_23 IOC5R<3:0> IOC4R<3:0> E34h RPINR20_21 IOC3R<3:0> IOC2R<3:0> E33h RPINR18_19 IOC1R<3:0> IOC0R<3:0> E32h RPINR16_17 ECCP3R<3:0> ECCP2R<3:0> E31h RPINR14_15 ECCP1R<3:0> FLT0R<3:0> E30h RPINR12_13 SS2R<3:0> SDI2R<3:0> E2Fh RPINR10_11 SCK2R<3:0> SS1R<3:0> E2Eh RPINR8_9 SDI1R<3:0> SCK1R<3:0> E2Dh RPINR
PIC18F97J94 FAMILY TABLE 6-2: REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 E03h UEP4 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL E02h UEP3 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL E01h UEP2 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL E00h UEP1 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL DFFh UEP0 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL DFEh Unimplemented — — — — — — — — DFDh Unimp
PIC18F97J94 FAMILY 6.3.5 STATUS REGISTER The STATUS register, shown in Register 6-2, contains the arithmetic status of the ALU. The STATUS register can be the operand for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the write to these five bits is disabled. These bits are set or cleared according to the device logic.
PIC18F97J94 FAMILY 6.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. For more information, see Section 6.6 “Data Memory and the Extended Instruction Set”. While the program memory can be addressed in only one way, through the Program Counter, information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed.
PIC18F97J94 FAMILY 6.4.3.1 FSR Registers and the INDF Operand mapped in the SFR space, but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers: FSRnH and FSRnL.
PIC18F97J94 FAMILY 6.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value.
PIC18F97J94 FAMILY 6.6 Data Memory and the Extended Instruction Set 6.6.2 INSTRUCTIONS AFFECTED BY INDEXED LITERAL OFFSET MODE Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Using the Access Bank for many of the core PIC18 instructions introduces a new addressing mode for the data memory space. This mode also alters the behavior of Indirect Addressing using FSR2 and its associated operands.
PIC18F97J94 FAMILY FIGURE 6-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When a = 0 and f 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and FFFh. This is the same as locations, F60h to FFFh (Bank 15), of data memory. Locations below 060h are not available in this addressing mode.
PIC18F97J94 FAMILY 6.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower part of Access RAM (00h to 5Fh) is mapped. Rather than containing just the contents of the bottom part of Bank 0, this mode maps the contents from Bank 0 and a user-defined “window” that can be located anywhere in the data memory space.
PIC18F97J94 FAMILY NOTES: DS30575A-page 142 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: A read from program memory is executed on 1 byte at a time. A write to program memory is executed on blocks of 64 bytes at a time or 2 bytes at a time.
PIC18F97J94 FAMILY FIGURE 7-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: The Table Pointer actually points to one of 64 holding registers; the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 7.5 “Writing to Flash Program Memory”. 7.
PIC18F97J94 FAMILY Register 7-1: EECON1: EEPROM CONTROL REGISTER 1 (ACCESS FA6h) U-0 U-0 R/W-0 R/W-0 R/W-x R/W-0 R/S-0 U-0 — — WWPROG FREE WRERR(1) WREN WR — bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 WWPROG: One Word-Wide Program bit 1 = Programs 2 bytes on the next WR command 0 = Programs 64 bytes
PIC18F97J94 FAMILY 7.2.2 TABLE LATCH REGISTER (TABLAT) 7.2.4 TABLE POINTER BOUNDARIES The Table Latch (TABLAT) is an 8-bit register mapped into the Special Function Register (SFR) space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. TBLPTR is used in reads, writes and erases of the Flash program memory. 7.2.
PIC18F97J94 FAMILY 7.3 Reading the Flash Program Memory The TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, the TBLPTR can be modified automatically for the next table read operation. The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. The internal program memory is typically organized by words.
PIC18F97J94 FAMILY 7.4 Erasing Flash Program Memory The minimum erase block is 256 words or 512 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 512 bytes of program memory is erased. The Most Significant 12 bits of the TBLPTR<21:10> point to the block being erased; TBLPTR<9:0> are ignored.
PIC18F97J94 FAMILY 7.5 Writing to Flash Program Memory The on-chip timer controls the write time. The write/ erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. The programming block is 32 words or 64 bytes. Programming one word or 2 bytes at a time is also supported. Note 1: Unlike previous PIC® MCUs, devices of the PIC18F97J94 family do not reset the holding registers after a write occurs.
PIC18F97J94 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the memory block, minus 1 BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF MOVLW MOVWF EECON1, WREN EECON1, FREE INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR INTCON, GIE D’8’ WRITE_COUNTER ; enable write to memory ; enable Erase operation ; disable interrupts MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'
PIC18F97J94 FAMILY 7.5.2 FLASH PROGRAM MEMORY WRITE SEQUENCE (WORD PROGRAMMING) The PIC18F97J94 family of devices has a feature that allows programming a single word (two bytes). This feature is enabled when the WWPROG bit is set. If the memory location is already erased, the following sequence is required to enable this feature: 1. 2. Load the Table Pointer register with the address of the data to be written. (It must be an even address.
PIC18F97J94 FAMILY 7.5.3 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 7.5.4 7.6 Flash Program Operation During Code Protection See Section 28.4.5 “Program Verification and Code Protection” for details on code protection of Flash program memory.
PIC18F97J94 FAMILY 8.0 EXTERNAL MEMORY BUS Note: The External Memory Bus implemented on 64-pin devices. is not The External Memory Bus (EMB) allows the device to access external memory devices (such as Flash, EPROM or SRAM) as program or data memory. It supports both 8 and 16-Bit Data Width modes, and three address widths of up to 20 bits. TABLE 8-1: The bus is implemented with 28 pins, multiplexed across four I/O ports.
PIC18F97J94 FAMILY 8.1 External Memory Bus Control The operation of the interface is controlled by the MEMCON register (Register 8-1). This register is available in all program memory operating modes, except Microcontroller mode. In this mode, the register is disabled and cannot be written to. The EBDIS bit (MEMCON<7>) controls the operation of the bus and related port functions.
PIC18F97J94 FAMILY 8.2 Address and Data Width 8.2.1 The PIC18F97J94 family of devices can be independently configured for different address and data widths on the same memory bus. Both address and data width are set by Configuration bits in the CONFIG5L register. As Configuration bits, this means that these options can only be configured by programming the device and are not controllable in software. The BW bit selects an 8-bit or 16-bit data bus width.
PIC18F97J94 FAMILY 8.3 Wait States While it may be assumed that external memory devices will operate at the microcontroller clock rate, this is often not the case. In fact, many devices require longer times to write or retrieve data than the time allowed by the execution of table read or table write operations. To compensate for this, the External Memory Bus can be configured to add a fixed delay to each table operation using the bus. Wait states are enabled by setting the WAIT Configuration bit.
PIC18F97J94 FAMILY 8.6.1 16-BIT BYTE WRITE MODE Figure 8-1 shows an example of 16-Bit Byte Write mode for PIC18F97J94 family devices. This mode is used for two separate 8-bit memories connected for 16-bit operation. This generally includes basic EPROM and Flash devices. It allows table writes to byte-wide external memories. FIGURE 8-1: During a TBLWT instruction cycle, the TABLAT data is presented on the upper and lower bytes of the AD<15:0> bus.
PIC18F97J94 FAMILY 8.6.2 16-BIT WORD WRITE MODE Figure 8-2 shows an example of 16-Bit Word Write mode for PIC18F97J94 family devices. This mode is used for word-wide memories, which includes some of the EPROM and Flash-type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory, and table writes to any type of word-wide external memories. This method makes a distinction between TBLWT cycles to even or odd addresses.
PIC18F97J94 FAMILY 8.6.3 16-BIT BYTE SELECT MODE Figure 8-3 shows an example of 16-Bit Byte Select mode. This mode allows table write operations to word-wide external memories with byte selection capability. This generally includes both word-wide Flash and SRAM devices. During a TBLWT cycle, the TABLAT data is presented on the upper and lower byte of the AD<15:0> bus. The WRH signal is strobed for each write cycle; the WRL pin is not used.
PIC18F97J94 FAMILY 8.6.4 16-BIT MODE TIMING The presentation of control signals on the External Memory Bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 8-4 and Figure 8-5.
PIC18F97J94 FAMILY 8.7 8-Bit Data Width Mode will enable one byte of program memory for a portion of the instruction cycle, then BA0 will change and the second byte will be enabled to form the 16-bit instruction word. The Least Significant bit of the address, BA0, must be connected to the memory devices in this mode. The Chip Enable (CE) signal is active at any time that the microcontroller accesses external memory, whether reading or writing.
PIC18F97J94 FAMILY 8.7.1 8-BIT MODE TIMING The presentation of control signals on the External Memory Bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 8-7 and Figure 8-8.
PIC18F97J94 FAMILY 8.8 Operation in Power-Managed Modes In Sleep and Idle modes, the microcontroller core does not need to access data; bus operations are suspended. The state of the external bus is frozen, with the address/data pins and most of the control pins holding at the same state they were in when the mode was invoked. The only potential changes are to the CE, LB and UB pins, which are held at logic high. In alternate, power-managed Run modes, the external bus continues to operate normally.
PIC18F97J94 FAMILY NOTES: DS30575A-page 164 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 9.0 8 x 8 HARDWARE MULTIPLIER 9.1 Introduction EXAMPLE 9-1: MOVF MULWF All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS register.
PIC18F97J94 FAMILY Example 9-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 9-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0).
PIC18F97J94 FAMILY 10.0 INTERRUPTS Members of the PIC18F97J94 family of devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress.
PIC18F97J94 FAMILY For external interrupt events, such as the INT pins or the PORTB interrupt-on-change, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one-cycle or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bits or the Global Interrupt Enable bit. Note: Do not use the MOVFF instruction to modify any of the Interrupt Control registers while any interrupt is enabled.
PIC18F97J94 FAMILY FIGURE 10-1: PIC18F97J94 FAMILY INTERRUPT LOGIC PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7,5:0> PIE2<7,5:0> IPR2<7,5:0> PIR3<7,5> PIE3<7,5> IPR3<7,5> PIR4<7:0> PIE4<7:0> IPR4<7:0> PIR5<7:0> PIE5<7:0> IPR5<7:0> Wake-up if in Idle or Sleep modes TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP Interrupt to CPU Vector to Location 0008h GIE/GIEH IPEN PIR6<7:0> PIE6<7:0> IPR6<7:0> IPEN PEIE/GIEL IPEN High-Priority Interrupt Gen
PIC18F97J94 FAMILY 10.4 INTCON Registers Note: The INTCON registers are readable and writable registers that contain various enable, priority and flag bits. REGISTER 10-1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
PIC18F97J94 FAMILY REGISTER 10-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP IOCIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External I
PIC18F97J94 FAMILY REGISTER 10-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low
PIC18F97J94 FAMILY 10.5 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are six Peripheral Interrupt Request (Flag) registers (PIR1 through PIR5). Note 1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>).
PIC18F97J94 FAMILY REGISTER 10-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF SSP2IF BCL2IF USBIF BCL1IF HLVDIF TMR3IF TMR3GIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (bit must be cle
PIC18F97J94 FAMILY REGISTER 10-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 TMR5GIF LCDIF RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR5GIF: TMR5 Gate Interrupt Flag bits 1 = TMR gate interrupt occurred (must be cleared in software) 0 = No TMR gate occurred bi
PIC18F97J94 FAMILY REGISTER 10-7: PIR4: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 4 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCP10IF CCP9IF CCP8IF CCP7IF CCP6IF CCP5IF CCP4IF ECCP3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CCP10IF: CCP10 Interrupt Flag bits Capture mode: 1 = A TMR register capture occurred (bit must be cleared in software) 0
PIC18F97J94 FAMILY REGISTER 10-7: PIR4: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 4 (CONTINUED) bit 3 CCP6IF: CCP6 Interrupt Flag bits Capture mode: 1 = A TMR register capture occurred (bit must be cleared in software) 0 = No TMR register capture occurred Compare mode: 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM mode: Not used in PWM mode.
PIC18F97J94 FAMILY REGISTER 10-8: PIR5: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 5 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — ACTORSIF ACTLOCKIF TMR8IF — TMR6IF TMR5IF TMR4IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 ACTORSIF: Active Clock Tuning Out-of-Range Interrupt Flag bit 1 = Active clock tuning out-of-range occurred 0 = Activ
PIC18F97J94 FAMILY REGISTER 10-9: PIR6: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 6 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 RC4IF TX4IF RC3IF TX3IF — CMP3IF CMP2IF CMP1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RC4IF: EUSART4 Receive Interrupt Flag bit 1 = The EUSART4 receive buffer is full (cleared by reading RCREG4) 0 = The EUSART4 receive b
PIC18F97J94 FAMILY 10.6 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are six Peripheral Interrupt Enable registers (PIE1 through PIE6). When IPEN (RCON<7>) = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
PIC18F97J94 FAMILY REGISTER 10-11: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE SSP2IE BCL2IE USBIE BCL1IE HLVDIE TMR3IE TMR3GIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit 1 = Enables
PIC18F97J94 FAMILY REGISTER 10-12: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMR5GIE LCDIE RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR5GIE: TMR5 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 LCDIE: LCD Ready Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 RC2IE: EUS
PIC18F97J94 FAMILY REGISTER 10-13: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCP10IE CCP9IE CCP8IE CCP7IE CCP6IE CCP5IE CCP4IE ECCP3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCP10IE: CCP10 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CCP9IE: CCP9 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 CCP8IE: CCP8 I
PIC18F97J94 FAMILY REGISTER 10-14: PIE5: PERIPHERAL INTERRUPT ENABLE REGISTER 5 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — ACTORSIE ACTLOCKIE TMR8IE — TMR6IE TMR5IE TMR4IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 ACTORSIE: Active Clock Tuning Out-of-Range Interrupt Enable bit 1 = Enables the active clock tuning out-of-range interrupt 0 =
PIC18F97J94 FAMILY REGISTER 10-15: PIE6: PERIPHERAL INTERRUPT ENABLE REGISTER 6 R/W-0 R/W-0 RC4IE TX4IE R/W-0 RC3IE R/W-0 U-0 R/W-0 R/W-0 R/W-0 TX3IE — CMP3IE CMP2IE CMP1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RC4IE: EUSART4 Receive Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 TX4IE: EUSART4 Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 RC34IE: E
PIC18F97J94 FAMILY 10.7 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are six Peripheral Interrupt Priority registers (IPR1 through IPR6). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit (RCON<7>) be set.
PIC18F97J94 FAMILY REGISTER 10-17: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP SSP2IP BCL2IP USBIP BCL1IP HLVDIP TMR3IP TMR3GIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority
PIC18F97J94 FAMILY REGISTER 10-18: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR5GIP LCDIP RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR5GIP: TMR5 Gate Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 LCDIP: LCD Ready Interrupt Priority bit 1 = High priority 0 = Low p
PIC18F97J94 FAMILY REGISTER 10-19: IPR4: PERIPHERAL INTERRUPT PRIORITY REGISTER 4 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CCP10IP CCP9IP CCP8IP CCP7IP CCP6IP CCP5IP CCP4IP ECCP3IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCP10IP: CCP10 Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CCP9IP: CCP9 Interrupt Priority bit 1 = High priority 0 = Low prior
PIC18F97J94 FAMILY REGISTER 10-20: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5 U-0 R/W-1 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 — ACTORSIP ACTLOCKIP TMR8IP — TMR6IP TMR5IP TMR4IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 ACTORSIP: Active Clock Tuning Out-of-Range Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 ACTLOCKIP: Acti
PIC18F97J94 FAMILY REGISTER 10-21: IPR6: PERIPHERAL INTERRUPT PRIORITY REGISTER 6 R/W-1 R/W-1 RC4IP TX4IP R/W-1 RC3IP R/W-1 U-O R/W-1 R/W-1 R/W-1 TX3IP — CMP3IP CMP2IP CMP1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RCP4IP: EUSART4 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 TX4IP: EUSART4 Transmit Interrupt Priority bit 1 = High priority 0 = Low
PIC18F97J94 FAMILY 10.8 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the bit that enables interrupt priorities (IPEN).
PIC18F97J94 FAMILY 10.9 INTx Pin Interrupts External interrupts on the RB0/INT0, RB1/INT1, RB2/INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge. If that bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxIE.
PIC18F97J94 FAMILY REGISTER 10-23: IOCP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IOCP7 IOCP6 IOCP5 IOCP4 IOCP3 IOCP2 IOCP1 IOCP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown IOCP<7:0>: Interrupt-on-Change Positive Edge Enable bits 1 = Interrupt-on-change is enabled on the pin for a rising edge; associated s
PIC18F97J94 FAMILY 10.12 Context Saving During Interrupts During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the Fast Return Stack. If a fast return from interrupt is not used (see Section 6.3 “Data Memory Organization”), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine (ISR). Depending on the user’s application, other registers also may need to be saved.
PIC18F97J94 FAMILY NOTES: DS30575A-page 196 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 11.0 I/O PORTS 11.1 Depending on the device selected and features enabled, there are up to eleven ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.
PIC18F97J94 FAMILY REGISTER 11-1: PADCFG1: PAD CONFIGURATION REGISTER 1(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RDPU REPU RFPU RGPU RHPU RJPU RKPU RLPU bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RDPU: PORTD Pull-up Enable bit 1 = PORTD pull-ups are enabled for any input pad 0 = All PORTD pull-ups are disabled bit 6 REPU: PORTE Pull-up Enable bit 1 = PORTE pull-u
PIC18F97J94 FAMILY 11.1.3 OPEN-DRAIN OUTPUTS FIGURE 11-2: The output pins for several peripherals are also equipped with a configurable, open-drain output option. This allows the peripherals to communicate with external digital logic, operating at a higher voltage level, without the use of level translators. USING THE OPEN-DRAIN OUTPUT (USART SHOWN AS EXAMPLE) 3.3V +5V PIC18F97J94 The open-drain option is implemented on the EUSARTs, the MSSPx modules (in SPI mode) and the CCP modules.
PIC18F97J94 FAMILY REGISTER 11-3: ODCON2: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CCP10OD CCP9OD CCP8OD CCP7OD CCP6OD CCP5OD CCP4OD ECCP3OD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCP10OD: CCP10 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 6 CCP9OD: CCP9 Open-
PIC18F97J94 FAMILY 11.2 PORTA, LATA and TRISA Registers PORTA is an 8-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISA and LATA. All PORTA pins have Schmitt Trigger input levels and full CMOS output drivers. RA<5:0> are multiplexed with analog inputs for the A/D Converter. The operation of the analog inputs as A/D Converter inputs is selected by clearing or setting the ANSELx control bits in the ANCON1 register.
PIC18F97J94 FAMILY TABLE 11-1: PORTA FUNCTIONS (CONTINUED) Pin Name RA3/AN3/VREF+/RP3 RA4/AN6/RP4/SEG14 RA5/AN4/RP5/LVDIN/ C1INA/C2INA/C3INA/ SEG15 RA6/RP6/CLKO/OSC2 RA7/RP10/CLKI/OSC1 Legend: Function TRIS Setting I/O I/O Type RA3 0 O DIG LATA<3> data output; not affected by analog input. 1 I ST PORTA<3> data input; disabled when analog input is enabled. AN3 1 I ANA A/D Input Channel 3. Default input configuration on POR; does not affect digital output.
PIC18F97J94 FAMILY 11.3 PORTB, LATB and TRISB Registers PORTB is an eight-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISB and LATB. All pins on PORTB are digital only. EXAMPLE 11-2: CLRF PORTB CLRF LATB MOVLW 0CFh MOVWF TRISB TABLE 11-2: ; ; ; ; ; ; ; ; ; ; ; ; RB0/INT0/CTED13/ RP8/VLCAP1 RB2/CTED1/RP14/ SEG9 RB3/CTED2/RP7/ SEG10 Legend: The RB<3:2> pins are multiplexed as CTMU edge inputs.
PIC18F97J94 FAMILY TABLE 11-2: PORTB FUNCTIONS (CONTINUED) Pin Name RB4/CTED3/RP12/ SEG11 RB5/CTED4/RP13/ SEG8 RB6/CTED5/PGC RB7/CTED6/PGD Legend: Function TRIS Setting I/O I/O Type RB4 0 O DIG LATB<4> data output. 1 I ST PORTB<4> data input. CTED3 1 I ST CTMU Edge 3 input. RP12 x x DIG Reconfigurable Pin 12 for PPS-Lite; TRIS must be set to match input/output of module. SEG11 0 O ANA LCD Segment 11 output; disables all other pin functions.
PIC18F97J94 FAMILY 11.4 PORTC, LATC and TRISC Registers PORTC is an eight-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISC and LATC. Only PORTC pins, RC2 through RC7, are digital only pins. The pins have Schmitt Trigger input buffers. When enabling peripheral functions, use care in defining TRIS bits for each PORTC pin. Some peripherals can override the TRIS bit to make a pin an output or input.
PIC18F97J94 FAMILY TABLE 11-3: Pin Name RC5/CTED10/ RP16/SEG12 RC6/CTED11/ UOE/RP18/ SEG27 RC7/CTED12/ RP19/SEG22 Legend: PORTC FUNCTIONS (CONTINUED) Function TRIS Setting I/O I/O Type RC5 0 O DIG LATC<5> data output. 1 I ST PORTC<5> data input. Description CTED10 1 I ST CTMU Edge 10 input. RP16 x x DIG Reconfigurable Pin 16 for PPS-Lite; TRIS must be set to match input/output of module. SEG12 0 O ANA LCD Segment 12 output; disables all other pin functions.
PIC18F97J94 FAMILY 11.5 PORTD, LATD and TRISD Registers PORTD is the low-order byte of the multiplexed Address/Data bus (AD<7:0>). The TRISD bits are also overridden. PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISD and LATD. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: These pins are configured as digital inputs on any device Reset.
PIC18F97J94 FAMILY TABLE 11-4: PORTD FUNCTIONS (CONTINUED) Pin Name Function TRIS Setting I/O I/O Type RD3/PSP3/ RP23/SEG3/AD3 RD3 0 O DIG LATD<3> data output. 1 I ST PORTD<3> data input. PSP3 x I/O RP23 x x RD4/PSP4/ RP24/SEG4/AD4 RD5/PSP5/ RP25/SDA2/ SEG5/AD5 RD6/PSP6/ RP26/SCL2/ SEG6/AD6 RD7/PSP7/ RP27/REFO2/ SEG7/AD7 Legend: Description ST/DIG Parallel Slave Port Data Bus Bit 3. DIG Reconfigurable Pin 23 for PPS-Lite; TRIS must be set to match input/output of module.
PIC18F97J94 FAMILY 11.6 PORTE, LATE and TRISE Registers PORTE is also multiplexed with the Parallel Slave Port address lines. RE2, RE1 and RE0 are multiplexed with the control signals, CS, WR and RD. PORTE is an eight-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISE and LATE. All pins on PORTE are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output.
PIC18F97J94 FAMILY TABLE 11-5: PORTE FUNCTIONS (CONTINUED) Pin Name RE3/REFO1/ RP33/COM0/ AD11 RE4/RP32/ COM1/AD12 RE5/RP37/ COM2/AD13 TRIS Setting I/O I/O Type RE3 0 O DIG 1 I ST PORTE<3> data input. REFO1 0 O DIG Reference Clock Output 1. RP33 x x DIG Reconfigurable Pin 33 for PPS-Lite; TRIS must be set to match input/output of module. ANA LCD Common 0 output; disables all other outputs. Description LATE<3> data output.
PIC18F97J94 FAMILY 11.7 PORTF, LATF and TRISF Registers PORTF is a 6-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISF and LATF. All pins on PORTF are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Pins, RF2 through RF6, may be used as comparator inputs or outputs by setting the appropriate bits in the CMCON register.
PIC18F97J94 FAMILY TABLE 11-6: PORTF FUNCTIONS (CONTINUED) Pin Name Function TRIS Setting I/O I/O Type RF5/RP35/C1INB/ AN10/CVREF/ SEG23 RF5 0 O DIG RF6/RP40/C1INA/ AN11/SEG24 RF7/RP38/AN5/ SEG25 Legend: Description LATF<5> data output. 1 I ST PORTF<5> data input. RP35 x x DIG Reconfigurable Pin 35 for PPS-Lite; TRIS must be set to match input/output of module. C1INB 1 I ANA Comparator 1 Input B. AN10 1 I ANA A/D Input Channel 10.
PIC18F97J94 FAMILY 11.8 PORTG, LATG and TRISG Registers EXAMPLE 11-7: CLRF PORTG width varies depending on pin count. For 64- and 80-pin devices, PORTG is a 6-bit wide, bidirectional port. For 100-pin devices, PORTG is an 8-bit wide bidirectional port. The corresponding Data Direction and Output Latch registers are TRISG and LATG. PORTG is multiplexed with the EUSART, and CCP, ECCP, Analog, Comparator, RTCC and Timer input functions (Table 11-7).
PIC18F97J94 FAMILY TABLE 11-7: Pin Name PORTG FUNCTIONS (CONTINUED) Function TRIS Setting I/O I/O Type RG3 0 O DIG LATG<3> data output; not affected by analog input. 1 I ST PORTG<3> data input; disabled when analog input is enabled. RP43 x x DIG Reconfigurable Pin 43 for PPS-Lite; TRIS must be set to match input/output of module. C3INB 1 I ANA Comparator 3 Input B. AN17 1 I ANA A/D Input Channel 17. Default input configuration on POR; does not affect digital output.
PIC18F97J94 FAMILY 11.9 Note: PORTH, LATH and TRISH Registers EXAMPLE 11-8: PORTH is available only on 80-pin and 100-pin devices. PORTH is an 8-bit wide, bidirectional I/O port. The corresponding Data Direction and Output Latch registers are TRISH and LATH. All pins on PORTH are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output.
PIC18F97J94 FAMILY TABLE 11-8: PORTH FUNCTIONS (CONTINUED) Pin Name Function TRIS Setting I/O I/O Type RH5/C2IND/AN 13/SEG41 RH5 0 O DIG LATH<5> data output; not affected by analog input. 1 I ST PORTH<5> data input; disabled when analog input is enabled. C2IND 1 I ANA Comparator 2 Input D. AN13 1 I ANA A/D Input Channel 13. Default input configuration on POR; does not affect digital output. SEG41 0 O ANA LCD Segment 41 output; disables all other pin functions.
PIC18F97J94 FAMILY 11.10 PORTJ, LATJ and TRISJ Registers Note: PORTJ is available only on 80-pin and 100-pin devices. PORTJ is an 8-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISJ and LATJ. All pins on PORTJ are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: These pins are configured as digital inputs on any device Reset.
PIC18F97J94 FAMILY TABLE 11-9: PORTJ FUNCTIONS (CONTINUED) Pin Name Function TRIS Setting I/O I/O Type RJ6/SEG37/LB RJ6 0 O DIG 1 I ST 0 O ANA SEG37 RJ7/SEG36/UB Legend: Description LATJ<6> data output. PORTJ<6> data input. LCD Segment 37 output; disables all other pin functions. LB x O DIG External Memory Bus Lower Byte (LB) signal. RJ7 0 O DIG LATJ<7> data output. 1 I ST SEG36 0 O ANA LCD Segment 36 output; disables all other pin functions. PORTJ<7> data input.
PIC18F97J94 FAMILY 11.11 PORTK, LATK and TRISK Registers Note: PORTK is available only on 100-pin devices. PORTK is an 8-bit wide, bidirectional port. The corresponding Data Direction and Output Latch registers are TRISK and LATK. All pins on PORTK are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Each of the PORTK pins has a weak internal pull-up.
PIC18F97J94 FAMILY 11.12 PORTL, LATL and TRISL Registers Note: The pull-ups are provided to keep the inputs at a known state for the external memory interface while powering up. A single control bit can turn off all the pull-ups. This is performed by clearing bit, RLPU (PADCFG<0>). PORTL is available only on 100-pin devices. The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on any device Reset. PORTL is an 8-bit wide, bidirectional port.
PIC18F97J94 FAMILY 11.13 Parallel Slave Port PORTD can function as an 8-bit-wide Parallel Slave Port (PSP), or microprocessor port, when control bit, PSPMODE (PSPCON<4>), is set. The port is asynchronously readable and writable by the external world through the RD control input pin (RE0/AD8/LCDBIAS1/RP28/RD) and WR control input pin (RE1/AD9/LCDBIAS2/RP29/WR). Note: The Parallel Slave Port is available only in Microcontroller mode. The PSP can directly interface to an 8-bit microprocessor data bus.
PIC18F97J94 FAMILY REGISTER 11-4: PSPCON: PARALLEL SLAVE PORT CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IBF OBF IBOV PSPMODE — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status b
PIC18F97J94 FAMILY FIGURE 11-5: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 11.14 Virtual PORT 11.15.2 This device includes a single virtual port, which is used to construct a logically addressed 8-bit PORT from 8 physically unrelated pins on the device. The virtual PORT is controlled through the PORTVR, LATVR and TRISVR registers. These function identically to the PORT, LAT and TRIS registers of the actual I/O ports. Refer to Section 11.1 “I/O Port Pin Capabilities” for more information.
PIC18F97J94 FAMILY FIGURE 11-6: STRUCTURE OF PORT SHARED WITH PPS PERIPHERALS Open-Drain Selection Output Multiplexers Peripheral Pin Select Output Function Select for the Pin Peripheral ‘n’ Output Enable Peripheral 2 Output Enable Peripheral 1 Output Enable I/O TRIS Enable Peripheral ‘n’ Output Data Peripheral 2 Output Data Peripheral 1 Output Data I/O LAT/PORT Data PIO Module Read TRIS Data Bus WR TRIS D Q CK Q n 1 0 I/O 0 1 n 1 0 I/O Pin TRIS Latch WR LAT/ WR PORT D Q CK Data Latch Read LA
PIC18F97J94 FAMILY 11.15.3 CONTROLLING PERIPHERAL PIN SELECT set associated with one of the remappable peripherals. Programming a given peripheral’s bit field with an RPn value maps the RPn pin to that peripheral. For any given device, the valid range of values for any of the bit fields corresponds to the maximum number of peripheral Pin Selections supported by the device.
PIC18F97J94 FAMILY TABLE 11-12: RPINR REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RPINR52_53 PBIO7R3 PBIO7R2 PBIO7R1 PBIO7R0 PBIO6R3 PBIO6R2 PBIO6R1 PBIO6R0 RPINR50_51 PBIO5R3 PBIO5R2 PBIO5R1 PBIO5R0 PBIO4R3 PBIO4R2 PBIO4R1 PBIO4R0 RPINR48_49 PBIO3R3 PBIO3R2 PBIO3R1 PBIO3R0 PBIO2R3 PBIO2R2 PBIO2R1 PBIO2R0 RPINR46_47 PBIO1R3 PBIO1R2 PBIO1R1 PBIO1R0 PBIO0R3 PBIO0R2 PBIO0R1 PBIO0R0 RPINR44_45 T5CKIR3 T5CKIR2 T5CKIR1 T5CKIR0 T5GR3 T5GR2 T5GR
PIC18F97J94 FAMILY TABLE 11-13: RPIN REGISTERS AND AVAILABLE FUNCTIONS PPS-Lite Input Peripheral Group 4n (1) To Map this signal (4) to the Associated RPIN Register SDI1 RPINR8_9<7:4> PPS-Lite Input Peripheral Group 4n + 1 (1) To Map this Signal (4) to the Associated RPIN Register SDI2 RPINR12_13<3:0> FLT0 RPINR14_15<3:0> INT1 RPINR26_27<3:0> IOC0 RPINR18_19<3:0> IOC1 RPINR18_19<7:4> IOC4 RPINR22_23<3:0> IOC5 RPINR22_23<7:4> MDCIN1 RPINR30_31<3:0> MDCIN2 RPINR30_31<7:4> T0CKI RPINR38_
PIC18F97J94 FAMILY TABLE 11-13: RPIN REGISTERS AND AVAILABLE FUNCTIONS (CONTINUED) PPS-Lite Input Peripheral Group 4n + 2 (1) To Map this Signal (4) to the Associated RPIN Register RPINR10_11<3:0> SS1 PPS-Lite Input Peripheral Group 4n + 3 (1) To Map this Signal (4) to the Associated RPIN Register SS2 RPINR12_13<7:4> INT2 RPINR26_27<7:4> INT3 RPINR28_29<3:0> IOC2 RPINR20_21<3:0> IOC3 RPINR20_21<7:4> IOC6 RPINR24_25<3:0> IOC7 RPINR24_25<7:4> MDMIN RPINR28_29<7:4> U1RX RPINR0_1<3:0> RPINR
PIC18F97J94 FAMILY FIGURE 11-8: MULTIPLEXING OF REMAPPABLE OUTPUT FOR RPn RPORn<3:0> I/O TRIS Setting 0 U1TX Output Enable 3 U1RTS Output Enable 4 Output Enable OC5 Output Enable I/O LAT/PORT Content 22 0 U1TX Output 3 U1RTS Output 4 RPn Output Data OC5 Output REGISTER 11-5: 22 RPORn_n: REMAPPED PERIPHERAL OUTPUT REGISTER n (FUNCTION MAPS TO PIN) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RPORn_3 RPORn_2 RPORn_1 RPORn_0 RPIRm_3 RPIRm_2 RPIRm_1 RPIRm_0 bit 7 bit 0 Legen
PIC18F97J94 FAMILY TABLE 11-14: PPS-LITE OUTPUT PPS-Lite Output Peripheral Group 4n PPS-Lite Output Peripheral Group 4n + 1 (1) To Map this RPn Pin (4) to the Associated RPOR Register (1) To Map this RPn Pin (4) to the Associated RPOR Register RP0 RPOR0_1<3:0> RP1 RPOR0_1<7:4> RP4 RPOR4_5<3:0> RP5 RPOR4_5<7:4> RP8 RPOR8_9<3:0> RP9 RPOR8_9<7:4> RP12 RPOR12_13<3:0> RP13 RPOR12_13<7:4> RP16 RPOR16_17<3:0> RP17 RPOR16_17<7:4> RP20 RPOR20_21<3:0> RP21 RPOR20_21<7:4> RP24 RPOR24_25<
PIC18F97J94 FAMILY TABLE 11-14: PPS-LITE OUTPUT (CONTINUED) PPS-Lite Output Peripheral Group 4n + 2 PPS-Lite Output Peripheral Group 4n +3 (1) To Map this RPn Pin (4) to the Associated RPOR Register (1) To Map this RPn Pin (4) to the Associated RPOR Register RP2 RPOR2_3<3:0> RP3 RPOR2_3<7:4> RP6 RPOR6_7<3:0> RP7 RPOR6_7<7:4> RP10 RPOR10_11<3:0> RP11 RPOR10_11<7:4> RP14 RPOR14_15<3:0> RP15 RPOR14_15<7:4> RP18 RPOR18_19<3:0> RP19 RPOR18_19<7:4> RP22 RPOR22_23<3:0> RP23 RPOR22_23<7
PIC18F97J94 FAMILY 11.15.4.1 Control Register Lock The contents of RPINRx and RPORx registers are constantly monitored in hardware by shadow registers. If an unexpected change in any of the registers occurs (such as cell disturbances caused by ESD or other external events), a Configuration Mismatch Reset will trigger. 11.15.4.2 Configuration Bit Pin Select Lock As an additional level of safety, the device can be configured to prevent more than one write session to the RPINRx and RPORx registers.
PIC18F97J94 FAMILY NOTES: DS30575A-page 234 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 12.0 DATA SIGNAL MODULATOR The Data Signal Modulator (DSM) is a peripheral which allows the user to mix a data stream, also known as a modulator signal, with a carrier signal to produce a modulated output. Both the carrier and the modulator signals are supplied to the DSM module, either internally from the output of a peripheral, or externally through an input pin.
PIC18F97J94 FAMILY FIGURE 12-1: SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR MDCH<3:0> VSS MDCIN1 MDCIN2 REFO1 Clock ECCP1 ECCP2 ECCP3 CCP4 CCP5 CCP6 CCP7 CCP8 CCP9 CCP10 System Clock REFO2 Clock 0000 0001 0010 0011 0100 0101 0110 CARH 0111 1000 1001 1010 1011 1100 1101 1110 1111 MDEN EN Data Signal Modulator MDCHPOL D SYNC Q 1 MDSRC<3:0> MDBIT MDMIN MSSP1 (SDO) MSSP2 (SDO) EUSART1 (TXX) EUSART2 (TXX) EUSART3 (TXX) EUSART4 (TXX) ECCP1 ECCP2 ECCP3 CCP4 CCP5 CCP6 CCP7 CCP8 0000 0001 0010 001
PIC18F97J94 FAMILY 12.1 DSM Operation The DSM module can be enabled by setting the MDEN bit in the MDCON register. Clearing the MDEN bit in the MDCON register disables the DSM module by automatically switching the Carrier High and Carrier Low signals to the VSS signal source. The Modulator signal source is also switched to the MDBIT in the MDCON register. This not only assures that the DSM module is inactive, but that it is also consuming the least amount of current. 12.
PIC18F97J94 FAMILY FIGURE 12-2: ON-OFF KEYING (OOK) SYNCHRONIZATION Carrier Low (CARL) Carrier High (CARH) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 MDCHSYNC = 1 MDCLSYNC = 1 MDCHSYNC = 0 MDCLSYNC = 0 MDCHSYNC = 0 MDCLSYNC = 1 FIGURE 12-3: NO SYNCHRONIZATION (MDCHSYNC = 0, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 0 Active Carrier State FIGURE 12-4: CARH CARL CARL CARH CARRIER HIGH SYNCHRONIZATION (MDCHSYNC = 1, MDCLSYNC = 0) Carrier High (CARH)
PIC18F97J94 FAMILY FIGURE 12-5: CARRIER LOW SYNCHRONIZATION (MDCHSYNC = 0, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 1 Active Carrier State FIGURE 12-6: CARH CARL CARH CARL FULL SYNCHRONIZATION (MDCHSYNC = 1, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) Falling edges used to sync MDCHSYNC = 1 MDCLSYNC = 1 Active Carrier State 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 12.5 Carrier Source Polarity Select The signal provided from any selected input source for the Carrier High and Carrier Low signals can be inverted. Inverting the signal for the Carrier High source is enabled by setting the MDCHPOL bit of the MDCARH register. Inverting the signal for the Carrier Low source is enabled by setting the MDCLPOL bit of the MDCARL register. 12.
PIC18F97J94 FAMILY REGISTER 12-1: R/W-0 MDCON: MODULATION CONTROL REGISTER R/W-0 MDEN MDOE R/W-1 MDSLR R/W-0 MDOPOL R/W-0 MDOUT (2) U-0 U-0 R/W-0 — — MDBIT(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MDEN: Modulator Module Enable bit 1 = Modulator module is enabled and mixing input signals 0 = Modulator module is disabled and has no output bit 6 MDOE: Modulator Module Pin Ou
PIC18F97J94 FAMILY REGISTER 12-2: MDSRC: MODULATION SOURCE CONTROL REGISTER R/W-x U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x MDSODIS — — — MDSRC3 MDSRC2 MDSRC1 MDSRC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MDSODIS: Modulation Source Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDMS<3:0>) is disabled 0 = Output signal dr
PIC18F97J94 FAMILY REGISTER 12-3: R/W-x MDCARH: MODULATION CARRIER HIGH CONTROL REGISTER R/W-x MDCHODIS MDCHPOL R/W-x U-0 R/W-x R/W-x R/W-x R/W-x MDCHSYNC — MDCH3(1) MDCH2(1) MDCH1(1) MDCH0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MDCHODIS: Modulator Carrier High Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDCH<3
PIC18F97J94 FAMILY REGISTER 12-4: R/W-x MDCARL: MODULATION CARRIER LOW CONTROL REGISTER R/W-x MDCLODIS MDCLPOL R/W-x U-0 R/W-x R/W-x R/W-x R/W-x MDCLSYNC — MDCL3(1) MDCL2(1) MDCL1(1) MDCL0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MDCLODIS: Modulator Carrier Low Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDCL<3:0
PIC18F97J94 FAMILY 13.
PIC18F97J94 FAMILY 13.1 LCD Registers The LCDCON register, shown in Register 13-1, controls the overall operation of the module. Once the module is configured, the ON (LCDCON<15>) bit is used to enable or disable the LCD module. The LCD panel can also operate during Sleep by clearing the SLPEN (LCDCON<6>) bit.
PIC18F97J94 FAMILY REGISTER 13-2: LCDREG: LCD CHARGE PUMP CONTROL REGISTER R/W-0 U-0 RW-1 RW-1 RW-1 RW-1 RW-0 RW-0 CPEN — BIAS2 BIAS1 BIAS0 MODE13 CLKSEL1 CLKSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CPEN: 3.6V Charge Pump Enable bit 1 = The regulator generates the highest (3.
PIC18F97J94 FAMILY REGISTER 13-3: LCDPS: LCD PHASE REGISTER R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WFT: Waveform Type Select bit 1 = Type-B waveform (phase changes on each frame boundary) 0 = Type-A waveform (phase changes within each common type) bit 6 BIASMD: Bias Mode
PIC18F97J94 FAMILY 13.2 LCD Segment Pins Configuration The LCDSEx registers configure the functions of the port pins. Setting the segment enable bit for a particular segment configures that pin as an LCD driver. There TABLE 13-1: are four LCD Segment Enable registers, as shown in Table 13-1. The prototype LCDSEx register is shown in Register 13-4.
PIC18F97J94 FAMILY REGISTER 13-5: LCDDATAx: LCD DATA x REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 S(n)Cy S(n)Cy S(n)Cy S(n)Cy S(n)Cy S(n)Cy S(n)Cy S(n)Cy bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 S(n)Cy: Pixel On bits For registers LCDDATA0 through LCDDATA7: n = (0-63), y = 0 For registers LCDDATA8 through LCDDATA15: n = (0-63), y = 1 For registers LCDDATA16
PIC18F97J94 FAMILY 13.3 LCD Clock Source Selection The LCD driver module has three possible clock sources: • FRC/8192 • SOSC Clock/32 The third clock source is a 31.25 kHz internal LPRC Oscillator/32 that provides approximately 1 kHz output. The second and third clock sources may be used to continue running the LCD while the processor is in Sleep. These clock sources are selected through the bits, CS<1:0> (LCDCON<4:3>).
PIC18F97J94 FAMILY 13.4 LCD Bias Types 13.5 The LCD module can be configured in one of three bias types: Internal Resistor Biasing This mode does not use external resistors, but rather internal resistor ladders that are configured to generate the bias voltage. • Static bias (two voltage levels: VSS and VDD) • 1/2 bias (three voltage levels: VSS, 1/2 VDD and VDD) • 1/3 bias (four voltage levels: VSS, 1/3 VDD, 2/3 VDD and VDD) The internal reference ladder actually consists of three separate ladders.
PIC18F97J94 FAMILY FIGURE 13-3: LCD BIAS INTERNAL RESISTOR LADDER CONNECTION DIAGRAM DD VVDD VDDCORE 3x Band Gap LCDIRS LCDIRE LCDCST<2:0> VLCD3PE LCDBIAS3 VLCD2PE LCDBIAS2 VLCD1PE LCDBIAS1 Low Resistor Ladder Medium Resistor Ladder High Resistor Ladder A Power Mode B Power Mode LRLAT<2:0> LRLAP<1:0> LRLBP<1:0> There are two power modes, designated as “Mode A” and “Mode B”. Mode A is set by the LRLAP<1:0> bits and Mode B by the LRLB<1:0> bits.
PIC18F97J94 FAMILY 13.5.1 AUTOMATIC POWER MODE SWITCHING (LCDREFL<2:0>) select how long or if the Mode A is active. Mode B Power mode is active for the remaining time before the segments or commons change again. As an LCD segment is electrically only a capacitor, current is drawn only during the interval when the voltage is switching. To minimize total device current, the LCD reference ladder can be operated in a different power mode for the transition portion of the duration.
PIC18F97J94 FAMILY 13.5.2 CONTRAST CONTROL The LCD contrast control circuit consists of a 7-tap resistor ladder, controlled by the LCDCSTx bits (see Figure 13-5) FIGURE 13-5: INTERNAL REFERENCE AND CONTRAST CONTROL BLOCK DIAGRAM 7 Stages VDD R R R R Analog MUX 7 0 To Top of Reference Ladder LCDCST<2:0> 3 Internal Reference 13.5.3 Contrast Control INTERNAL REFERENCE Under firmware control, an internal reference for the LCD bias voltages can be enabled.
PIC18F97J94 FAMILY REGISTER 13-6: LCDREF: LCD REFERENCE LADDER CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LCDIRE — LCDCST2 LCDCST1 LCDCST0 VLCD3PE VLCD2PE VLCD1PE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 LCDIRE: LCD Internal Reference Enable bit 01 = Internal LCD reference is enabled and connected to the internal contrast control cir
PIC18F97J94 FAMILY REGISTER 13-7: LCDRL: LCD REFERENCE LADDER CONTROL REGISTER LOW R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 LRLAP1 LRLAP0 LRLBP1 LRLBP0 — LRLAT2 LRLAT1 LRLAT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 LRLAP<1:0>: LCD Reference Ladder A Time Power Control bits During Time Interval A: 11 = Internal LCD reference ladder is powered in
PIC18F97J94 FAMILY 13.5.5 LCD BIAS GENERATION 13.5.7 The LCD driver module is capable of generating the required bias voltages for LCD operation with a minimum of external components. This includes the ability to generate the different voltage levels required by the different bias types that are required by the LCD. The driver module can also provide bias voltages, both above and below microcontroller VDD, through the use of an on-chip LCD voltage regulator. 13.5.
PIC18F97J94 FAMILY 13.6 BIAS CONFIGURATIONS PIC18F97J94 family devices have four distinct circuit configurations for LCD bias generation: • • • • M0: Regulator with Boost M1: Regulator without Boost M2: Resistor Ladder with Software Contrast M3: Resistor Ladder with Hardware Contrast 13.6.1 M0 (REGULATOR WITH BOOST) In M0 operation, the LCD charge pump feature is enabled. This allows the regulator to generate voltages up to +3.6V to the LCD (as measured at LCDBIAS3).
PIC18F97J94 FAMILY FIGURE 13-6: LCD REGULATOR CONNECTIONS FOR M0 AND M1 CONFIGURATIONS PIC18F97J94 VLCAP1 VLCAP2 LCDBIAS3 LCDBIAS2 LCDBIAS1 LCDBIAS0 Mode 0 (VBIAS up to 3.6V) Note 1: CFLY 0.47 F(1) 0.47 F(1) VDD C3 0.47 F(1) C2 0.47 F(1) C1 0.47 F(1) C0 0.47 F(1) C2 0.47 F(1) C1 0.47 F(1) C0 0.47 F(1) Mode 1 (VBIAS VDD) These values are provided for design guidance only; they should be optimized for the application by the designer based on the actual LCD specifications.
PIC18F97J94 FAMILY 13.6.3 M2 (EXTERNAL RESISTOR LADDER WITH SOFTWARE CONTRAST) LCDBIAS0. The bias type is determined by the voltages on the LCDBIAS pins, which are controlled by the configuration of the resistor ladder. Most applications, using M2, will use a 1/3 or 1/2 bias type. While static bias can also be used, it offers extremely limited contrast range and additional current consumption over other bias generation modes. M2 operation also uses the LCD regulator but disables the charge pump.
PIC18F97J94 FAMILY 13.6.4 M3 (HARDWARE CONTRAST) In M3, the LCD regulator is completely disabled. Like M2, LCD bias levels are tied to VDD and are generated using an external divider. The difference is that the internal voltage reference is also disabled and the bottom of the ladder is tied to ground (VSS); see Figure 138. The value of the resistors, and the difference between VSS and VDD, determine the contrast range; no software adjustment is possible.
PIC18F97J94 FAMILY 13.7 Design Considerations for the LCD Charge Pump When designing applications that use the LCD regulator with the charge pump enabled, users must always consider both the dynamic current and RMS (static) current requirements of the display, and what the charge pump can deliver.
PIC18F97J94 FAMILY 13.
PIC18F97J94 FAMILY 13.12 LCD Waveform Generation LCD waveform generation is based on the philosophy that the net AC voltage across the dark pixel should be maximized and the net AC voltage across the clear pixel should be minimized. The net DC voltage across any pixel should be zero. The COM signal represents the time slice for each common, while the SEG contains the pixel data. The pixel signal (COM-SEG) will have no DC component and can take only one of the two rms values.
PIC18F97J94 FAMILY FIGURE 13-10: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE V2 COM0 V1 V0 COM1 V2 COM0 COM1 V1 V0 V2 V1 SEG0 V0 SEG0 SEG1 SEG2 SEG3 V2 V1 SEG1 V0 V2 V1 V0 COM0-SEG0 -V1 -V2 V2 V1 V0 COM0-SEG1 -V1 -V2 1 Frame DS30575A-page 266 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY FIGURE 13-11: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE V2 V1 COM0 COM1 V0 COM0 V2 COM1 V1 V0 V2 SEG0 V1 SEG0 SEG1 SEG2 SEG3 V0 V2 SEG1 V1 V0 V2 V1 V0 COM0-SEG0 -V1 -V2 V2 V1 V0 COM0-SEG1 -V1 -V2 2 Frames 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY FIGURE 13-12: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE V3 V2 COM0 V1 COM1 V0 V3 COM0 V2 COM1 V1 V0 V3 V2 SEG0 V1 V0 SEG0 SEG1 SEG2 SEG3 V3 V2 SEG1 V1 V0 V3 V2 V1 V0 COM0-SEG0 -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 -V1 -V2 1 Frame DS30575A-page 268 -V3 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY FIGURE 13-13: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE V3 V2 COM0 V1 COM1 V0 V3 COM0 V2 COM1 V1 V0 V3 V2 SEG0 V1 V0 SEG0 SEG1 SEG2 SEG3 V3 V2 SEG1 V1 V0 V3 V2 V1 V0 COM0-SEG0 -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 -V1 -V2 2 Frames 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY FIGURE 13-14: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE V2 COM0 V1 V0 COM2 V2 COM1 V1 V0 COM1 COM0 V2 COM2 V1 V0 V2 SEG0 SEG2 V1 SEG0 SEG1 SEG2 V0 V2 SEG1 V1 V0 V2 V1 V0 COM0-SEG0 -V1 -V2 V2 V1 V0 COM0-SEG1 -V1 -V2 1 Frame DS30575A-page 270 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY FIGURE 13-15: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE V2 COM0 V1 V0 COM2 V2 COM1 V1 COM1 V0 COM0 V2 COM2 V1 V0 V2 V1 V0 SEG0 SEG1 SEG2 SEG0 V2 SEG1 V1 V0 V2 V1 V0 COM0-SEG0 -V1 -V2 V2 V1 V0 COM0-SEG1 -V1 -V2 2 Frames 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY FIGURE 13-16: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE V3 V2 COM0 V1 V0 V3 COM2 V2 COM1 V1 COM1 V0 COM0 V3 V2 COM2 V1 V0 V3 V2 V1 V0 SEG0 SEG1 SEG2 SEG0 SEG2 V3 V2 SEG1 V1 V0 V3 V2 V1 V0 COM0-SEG0 -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 -V1 -V2 -V3 1 Frame DS30575A-page 272 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY FIGURE 13-17: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE V3 V2 COM0 V1 V0 V3 COM2 V2 COM1 V1 COM1 V0 COM0 V3 V2 COM2 V1 V0 V3 V2 V1 V0 SEG0 SEG1 SEG2 SEG0 V3 V2 SEG1 V1 V0 V3 V2 V1 V0 COM0-SEG0 -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 -V1 -V2 -V3 2 Frames 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY FIGURE 13-18: TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 COM3 V3 V2 V1 V0 SEG0 V3 V2 V1 V0 SEG1 V3 V2 V1 V0 COM0-SEG0 V3 V2 V1 V0 -V1 -V2 -V3 COM0-SEG1 V3 V2 V1 V0 -V1 -V2 -V3 SEG0 SEG1 COM0 1 Frame DS30575A-page 274 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY FIGURE 13-19: TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 COM3 V3 V2 V1 V0 SEG0 V3 V2 V1 V0 SEG1 V3 V2 V1 V0 COM0-SEG0 V3 V2 V1 V0 -V1 -V2 -V3 COM0-SEG1 V3 V2 V1 V0 -V1 -V2 -V3 SEG0 SEG1 COM0 2 Frames 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY FIGURE 13-20: TYPE-A WAVEFORMS IN 1/8 MUX, 1/3 BIAS DRIVE COM4 COM0 COM5 COM3 COM7 COM2 COM6 COM1 COM1 COM0 COM2 COM7 SEG0 SEG0 COM0-SEG0 COM1-SEG0 DS30575A-page 276 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 V3 V2 V1 V0 -V1 -V2 -V3 V3 V2 V1 V0 -V1 -V2 -V3 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY FIGURE 13-21: TYPE-B WAVEFORMS IN 1/8 MUX, 1/3 BIAS DRIVE COM4 COM3 COM5 COM0 COM7 COM2 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 COM6 COM1 COM0 COM7 SEG0 SEG0 COM0 - SEG0 COM1 - SEG0 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 13.13 LCD Interrupts When the LCD driver is running with Type-B waveforms, and the LMUX<2:0> bits are not equal to ‘000’, there are some additional issues. The LCD timing generation provides an interrupt that defines the LCD frame timing. This interrupt can be used to coordinate the writing of the pixel data with the start of a new frame, which produces a visually crisp transition of the image.
PIC18F97J94 FAMILY 13.14 Configuring the LCD Module 13.15 Operation During Sleep To configure the LCD module. The LCD module can operate during Sleep. The selection is controlled by the SLPEN bit (LCDCONL<6>). Setting the SLPEN bit allows the LCD module to go to Sleep. Clearing the SLPEN bit allows the module to continue to operate during Sleep. 1. 2. 3. 4. 5. 6. 7. Select the frame clock prescale using bits, LP<3:0> (LCDPS<3:0>).
PIC18F97J94 FAMILY FIGURE 13-23: SLEEP ENTRY/EXIT WHEN SLPEN = 1 OR CS<1:0> = 00. V3 V2 V1 COM0 V0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 SEG0 2 Frames SLEEP Instruction Execution DS30575A-page 280 Wake-up 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 14.0 TIMER0 MODULE The Timer0 module incorporates the following features: • Software-selectable operation as a timer or counter in both 8-bit or 16-bit modes • Readable and writable registers • Dedicated 8-bit, software programmable prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow REGISTER 14-1: The T0CON register (Register 14-1) controls all aspects of the module’s operation, including the prescale selection.
PIC18F97J94 FAMILY 14.1 Timer0 Operation 14.2 Timer0 can operate in one of these two modes: TMR0H is not the actual high byte of Timer0 in 16-bit mode. It is actually a buffered version of the real high byte of Timer0, which is not directly readable nor writable (see Figure 14-2). TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L.
PIC18F97J94 FAMILY 14.3 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable. Its value is set by the PSA and T0PS<2:0> bits (T0CON<3:0>), which determine the prescaler assignment and prescale ratio. Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values from 1:2 through 1:256 in power-of-two increments are selectable.
PIC18F97J94 FAMILY 15.0 TIMER1/3/5 MODULES The Timer1/3/5 timer/counter modules incorporate these features: • Software-selectable operation as a 16-bit timer or counter • Readable and writable eight-bit registers (TMRxH and TMRxL) • Selectable clock source (internal or external) with device clock or SOSC Oscillator internal options • Interrupt-on-overflow • Module Reset on ECCP Special Event Trigger A simplified block diagram of the Timer1/3/5 module is shown in Figure 15-1.
PIC18F97J94 FAMILY REGISTER 15-1: TxCON: TIMERx CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMRxCS1 TMRxCS0 TxCKPS1 TxCKPS0 SOSCEN TxSYNC RD16 TMRxON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 TMRxCS<1:0>: Timerx Clock Source Select bits 11 = Timerx Clock source is INTOSC 10 = Timerx clock source depends on the SOSCEN bit: SOSCEN =
PIC18F97J94 FAMILY 15.1 Timer1/3/5 Gate Control Register The Timer1/3/5 Gate Control register (TxGCON), provided in Register 15-2, is used to control the Timerx gate.
PIC18F97J94 FAMILY 15.2 Timer1/3/5 Operation The operating mode is determined by the clock select bits, TMRxCSx (TxCON<7:6>). When the TMRxCSx bits are cleared (= 00), Timer1/3/5 increments on every internal instruction cycle (FOSC/4). When TMRxCSx = 01, the Timer1/3/5 clock source is the system clock (FOSC). When it is ‘10’, Timer1/3/5 works as a counter from the external clock from the TxCKI pin (on the rising edge after the first falling edge) or the SOSC Oscillator.
PIC18F97J94 FAMILY 15.3 Timer1/3/5 16-Bit Read/Write Mode Timer1/3/5 can be configured for 16-bit reads and writes (see Figure 15-3). When the RD16 control bit (TxCON<1>) is set, the address for TMRxH is mapped to a buffer register for the high byte of Timer1/3/5. A read from TMRxL will load the contents of the high byte of Timer1/3/5 into the Timerx High Byte Buffer register.
PIC18F97J94 FAMILY 15.5 Timer1/3/5 Gates When Timerx Gate Enable mode is enabled, Timer1/3/5 will increment on the rising edge of the Timer1/3/5 clock source. When Timerx Gate Enable mode is disabled, no incrementing will occur and Timer1/3/5 will hold the current count. See Figure 15-2 for timing details. Timer1/3/5 can be configured to count freely or the count can be enabled and disabled using the Timer1/3/5 gate circuitry. This is also referred to as the Timer1/3/5 gate count enable.
PIC18F97J94 FAMILY 15.5.2 TIMER1/3/5 GATE SOURCE SELECTION The Timer1/3/5 gate source can be selected from one of four different sources. Source selection is controlled by the TxGSS<1:0> bits (TxGCON<1:0>). The polarity for each available source is also selectable and is controlled by the TxGPOL bit (TxGCON <6>).
PIC18F97J94 FAMILY 15.5.4 TIMER1/3/5 GATE SINGLE PULSE MODE No other gate events will be allowed to increment Timer1/3/5 until the TxGGO/TxDONE bit is once again set in software. When Timer1/3/5 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1/3/5 Gate Single Pulse mode is first enabled by setting the TxGSPM bit (TxGCON<4>). Next, the TxGGO/TxDONE bit (TxGCON<3>) must be set. Clearing the TxGSPM bit also will clear the TxGGO/ TxDONE bit.
PIC18F97J94 FAMILY FIGURE 15-5: TIMER1/3/5 GATE SINGLE PULSE AND TOGGLE COMBINED MODE TMRxGE TxGPOL TxGSPM TxGTM TxGGO/ Cleared by Hardware on Falling Edge of TxGVAL Set by Software TxDONE Counting Enabled on Rising Edge of TxG TxG_IN TxCKI TxGVAL Timer1/3/5 TMRxGIF 15.5.5 N Cleared by Software TIMER1/3/5 GATE VALUE STATUS When Timer1/3/5 gate value status is utilized, it is possible to read the most current level of the gate control value.
PIC18F97J94 FAMILY 15.6 Timer1/3/5 Interrupt The TMRx register pair (TMRxH:TMRxL) increments from 0000h to FFFFh and overflows to 0000h. The Timerx interrupt, if enabled, is generated on overflow and is latched in the interrupt flag bit, TMRxIF. Table 15-3 gives each module’s flag bit. TABLE 15-3: TIMER1/3/5 INTERRUPT FLAG BITS Timer Module Flag Bit 1 PIR1<0> 3 PIR2<1> 5 PIR5<1> This interrupt can be enabled or disabled by setting or clearing the TMRxIE bit, respectively.
PIC18F97J94 FAMILY 16.
PIC18F97J94 FAMILY REGISTER 16-1: TxCON: TIMERx CONTROL REGISTER (TIMER2/4/6/8) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TxOUTPS3 TxOUTPS2 TxOUTPS1 TxOUTPS0 TMRxON TxCKPS1 TxCKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 TxOUTPS<3:0>: Timerx Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16
PIC18F97J94 FAMILY NOTES: DS30575A-page 296 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 17.
PIC18F97J94 FAMILY 17.
PIC18F97J94 FAMILY 17.1.
PIC18F97J94 FAMILY REGISTER 17-2: RTCCAL: RTCC CALIBRATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown CAL<7:0>: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every minute . . .
PIC18F97J94 FAMILY Register 17-3: R/W-0 R/W-0 RTCCON2: RTC CONFIGURATION REGISTER 2(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PWCEN(1) PWCPOL(1) PWCCPRE(1) PWCSPRE(1) RTCCLKSEL1 RTCCLKSEL0 RTCSECSEL1 RTCSECSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PWCEN: Power Control Enable bit(1) 1 = Power control is enabled 0 = Power control is disabled bit 6 PWCPOL: Power
PIC18F97J94 FAMILY REGISTER 17-4: ALRMCFG: ALARM CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 00h and CHIME = 0) 0 = A
PIC18F97J94 FAMILY REGISTER 17-5: ALRMRPT: ALARM REPEAT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 17.1.2 x = Bit is unknown ARPT<7:0>: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times . . .
PIC18F97J94 FAMILY REGISTER 17-7: YEAR: YEAR VALUE REGISTER(1) (RTCVALL when RTCPTR<1:0> = 11) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit bits Contains a value from 0 to 9.
PIC18F97J94 FAMILY REGISTER 17-9: DAY: DAY VALUE REGISTER(1) (RTCVALL when RTCPTR<1:0> = 10) U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN<1:0>: Binary Coded Decimal value of Day’s Tens Digit bits Contains a value from
PIC18F97J94 FAMILY REGISTER 17-12: MINUTE: MINUTE VALUE REGISTER (RTCVALH when RTCPTR<1:0> = 00) U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a
PIC18F97J94 FAMILY 17.1.3 ALRMVALH AND ALRMVALL REGISTER MAPPINGS The registers described in this section are the targets or sources for writes or reads to the ALRMVALH and ALRMVALL in the order they will appear when accessed through the ALRMCFG pointer. For more information on ALRMVAL register mapping, please see Section 17.2.8 “Register Mapping”.
PIC18F97J94 FAMILY REGISTER 17-16: ALRMWD: ALARM WEEKDAY VALUE REGISTER(1) (ALRMVALH WHEN ALRMPTR<1:0> = 01) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6.
PIC18F97J94 FAMILY REGISTER 17-18: ALRMMIN: ALARM MINUTES VALUE REGISTER (ALRMVALH when ALRMPTR<1:0> = 00) U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits
PIC18F97J94 FAMILY 17.1.4 17.2 RTCEN BIT WRITE RTCWREN (RTCCON1<5>) must be set before a write to RTCEN can take place. Any write to the RTCEN bit, while RTCWREN = 0, will be ignored. Like the RTCEN bit, the RTCVALH and RTCVALL registers can only be written to when RTCWREN = 1. A write to these registers, while RTCWREN = 0, will be ignored. FIGURE 17-2: 17.2.1 Operation REGISTER INTERFACE The register interface for the RTCC and alarm values is implemented using the Binary Coded Decimal (BCD) format.
PIC18F97J94 FAMILY 17.2.2 CLOCK SOURCE Calibration of the crystal can be done through this module to yield an error of 3 seconds or less per month. (For further details, see Section 17.2.9 “Calibration”.) As mentioned earlier, the RTCC module is intended to be clocked by an external Real-Time Clock (RTC) crystal, oscillating at 32.768 kHz, but an internal oscillator can be used. The RTCC clock selection is decided by the RTCOSC bit (CONFIG3L<0>). FIGURE 17-4: CLOCK SOURCE MULTIPLEXING 32.
PIC18F97J94 FAMILY 17.2.4 LEAP YEAR Since the year range on the RTCC module is 2000 to 2099, the leap year calculation is determined by any year divisible by four in the above range. Only February is affected in a leap year. February will have 29 days in a leap year and 28 days in any other year. 17.2.5 GENERAL FUNCTIONALITY All Timer registers containing a time value of seconds or greater are writable.
PIC18F97J94 FAMILY TABLE 17-4: 17.3 ALRMVAL REGISTER MAPPING ALRMPTR<1:0> 00 The Alarm features and characteristics are: Alarm Value Register Window ALRMVALH ALRMVALL ALRMMIN ALRMSEC 01 ALRMWD ALRMHR 10 ALRMMNTH ALRMDAY 11 — — 17.2.9 CALIBRATION The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than three seconds per month.
PIC18F97J94 FAMILY FIGURE 17-5: ALARM MASK SETTINGS Alarm Mask Setting AMASK<3:0> Day of the Week Month Day Hours Minutes Seconds 0000 – Every half second 0001 – Every second 0010 – Every 10 seconds s 0011 – Every minute s s m s s m m s s 0100 – Every 10 minutes 0101 – Every hour 0110 – Every day 0111 – Every week d 1000 – Every month 1001 – Every year(1) Note 1: m m h h m m s s h h m m s s d d h h m m s s d d h h m m s s Annually, except when configured
PIC18F97J94 FAMILY FIGURE 17-6: TIMER PULSE GENERATION RTCEN bit ALRMEN bit RTCC Alarm Event RTCC Pin 17.4 Sleep Mode 17.5.2 POWER-ON RESET (POR) The timer and alarm continue to operate while in Sleep mode. The operation of the alarm is not affected by Sleep, as an alarm event can always wake-up the CPU. The RTCCON1 and ALRMRPT registers are reset only on a POR. Once the device exits the POR state, the clock registers should be reloaded with the desired values.
PIC18F97J94 FAMILY 17.6 Register Maps Table 17-5, Table 17-6 and Table 17-7 summarize the registers associated with the RTCC module.
PIC18F97J94 FAMILY 18.0 ENHANCED CAPTURE/COMPARE/PWM (ECCP) MODULE PIC18F97J94 family devices have three Enhanced Capture/Compare/PWM (ECCP) modules: ECCP1, ECCP2 and ECCP3. These modules contain a 16-bit register, which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register.
PIC18F97J94 FAMILY REGISTER 18-1: R/W-0 PxM1 CCPxCON: ENHANCED CAPTURE/COMPARE/PWM x CONTROL R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 PxM<1:0>: Enhanced PWM Output Configuration bits If CCPxM<3:2> = 00, 01, 10: xx = PxA is assigned as the capture/compare input/output;
PIC18F97J94 FAMILY REGISTER 18-2: CCPTMRS0: CCP TIMER SELECT 0 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C3TSEL1 C3TSEL0 C2TSEL2 C2TSEL1 C2TSEL0 C1TSEL2 C1TSEL1 C1TSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 C3TSEL<1:0>: CCP3 Timer Selection bits 00 = CCP3 is based off of TMR1/TMR2 01 = CCP3 is based off of TMR3/TMR4 10 = CCP3 is based off of TMR3/TMR6 1
PIC18F97J94 FAMILY In addition to the expanded range of modes available through the CCPxCON, the ECCP modules have three additional registers associated with Enhanced PWM operation, Pulse Steering Control and auto-shutdown features. They are: • ECCPxDEL – Enhanced PWM x Control • PSTRxCON – Pulse Steering x Control • ECCPxAS – Auto-Shutdown x Control 18.1 ECCP Outputs and Configuration The Enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode.
PIC18F97J94 FAMILY 18.2 Capture Mode 18.2.2 In Capture mode, the CCPRxH:CCPRxL register pair captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on the corresponding ECCPx pin.
PIC18F97J94 FAMILY 18.3 Compare Mode 18.3.2 In Compare mode, the 16-bit CCPRx register value is constantly compared against the Timer register pair value selected in the CCPTMR0 register. When a match occurs, the ECCPx pin can be: • • • • Driven high Driven low Toggled (high-to-low or low-to-high) Unchanged (that is, reflecting the state of the I/O latch) The action on the pin is based on the value of the mode select bits (CCPxM<3:0>). At the same time, the interrupt flag bit, CCPxIF, is set. 18.3.
PIC18F97J94 FAMILY 18.4 PWM (Enhanced Mode) The PWM outputs are multiplexed with I/O pins and are designated: PxA, PxB, PxC and PxD. The polarity of the PWM pins is configurable and is selected by setting the CCPxM bits in the CCPxCON register appropriately. The Enhanced PWM mode can generate a PWM signal on up to four different output pins, with up to 10 bits of resolution.
PIC18F97J94 FAMILY TABLE 18-3: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode PxM<1:0> PxA PxB PxC PxD Single 00 Yes(1) Yes(1) Yes(1) Yes(1) Half-Bridge 10 Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes Note 1: Outputs are enabled by pulse steering in Single mode (see Register 18-5).
PIC18F97J94 FAMILY FIGURE 18-5: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) PxM<1:0> Signal PR2 + 1 Pulse Width 0 Period 00 (Single Output) PxA Modulated PxA Modulated 10 (Half-Bridge) Delay(1) Delay(1) PxB Modulated PxA Active 01 (Full-Bridge, Forward) PxB Inactive PxC Inactive PxD Modulated PxA Inactive 11 (Full-Bridge, Reverse) PxB Modulated PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPRxL<7
PIC18F97J94 FAMILY 18.4.1 HALF-BRIDGE MODE Since the PxA and PxB outputs are multiplexed with the PORT data latches, the associated TRIS bits must be cleared to configure PxA and PxB as outputs. In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the PxA pin, while the complementary PWM output signal is output on the PxB pin (see Figure 18-6).
PIC18F97J94 FAMILY 18.4.2 FULL-BRIDGE MODE In the Reverse mode, the PxC pin is driven to its active state and the PxB pin is modulated, while the PxA and PxD pins are driven to their inactive state, as provided in Figure 18-9. In Full-Bridge mode, all four pins are used as outputs. An example of a full-bridge application is provided in Figure 18-8. The PxA, PxB, PxC and PxD outputs are multiplexed with the port data latches.
PIC18F97J94 FAMILY FIGURE 18-9: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period PxA (2) Pulse Width PxB(2) PxC(2) PxD(2) (1) (1) Reverse Mode Period Pulse Width PxA(2) PxB(2) PxC(2) PxD(2) (1) Note 1: 2: (1) At this time, the TMR2 register is equal to the PR2 register. The output signal is shown as active-high. DS30575A-page 328 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 18.4.2.1 Direction Change in Full-Bridge Mode In Full-Bridge mode, the PxM1 bit in the CCPxCON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. A direction change is initiated in software by changing the PxM1 bit of the CCPxCON register.
PIC18F97J94 FAMILY FIGURE 18-11: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period PxA PxB PW PxC PxD PW TON External Switch C TOFF External Switch D Potential Shoot-Through Current Note 1: 18.4.3 All signals are shown as active-high. 2: TON is the turn-on delay of power switch QC and its driver. 3: TOFF is the turn-off delay of power switch QD and its driver.
PIC18F97J94 FAMILY When a shutdown event occurs, two things happen: Each pin pair may be placed into one of three states: • The ECCPxASE bit is set to ‘1’. The ECCPxASE will remain set until cleared in firmware or an auto-restart occurs. (See Section 18.4.5 “Auto-Restart Mode”.) • The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs (PxA/PxC and PxB/PxD).
PIC18F97J94 FAMILY FIGURE 18-12: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PxRSEN = 0) PWM Period Shutdown Event ECCPxASE bit PWM Activity Normal PWM Start of PWM Period 18.4.5 Shutdown Event Occurs AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PxRSEN bit (ECCPxDEL<7>).
PIC18F97J94 FAMILY 18.4.6 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 18-14: In half-bridge applications, where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period until one switch completely turns off.
PIC18F97J94 FAMILY REGISTER 18-4: ECCPxDEL: ENHANCED PWM CONTROL REGISTER x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxRSEN PxDC6 PxDC5 PxDC4 PxDC3 PxDC2 PxDC1 PxDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPxASE bit clears automatically once the shutdown event goes away; the PWM resta
PIC18F97J94 FAMILY REGISTER 18-5: R/W-0 CMPL1 PSTRxCON: PULSE STEERING CONTROL(1) R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 CMPL0 — STRSYNC STRD STRC STRB STRA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 CMPL<1:0>: Complementary Mode Output Assignment Steering Sync bits 00 = See STR 01 = PA and PB are selected as the complementary output pair 10 = PA and
PIC18F97J94 FAMILY FIGURE 18-16: SIMPLIFIED STEERING BLOCK DIAGRAM STRA(2) PxA Signal CCPxM1 PORT Data Output Pin(1) 1 0 TRIS STRB(2) CCPxM0 1 PORT Data 0 STRC Output Pin(1) CCPxM1 PORT Data Output Pin(1) 1 PORT Data Note 1: 2: The STRSYNC bit of the PSTRxCON register gives the user two choices for when the steering event will happen. When the STRSYNC bit is ‘0’, the steering event will happen at the end of the instruction that writes to the PSTRxCON register.
PIC18F97J94 FAMILY 18.4.8 OPERATION IN POWER-MANAGED MODES 18.4.8.1 Operation with Fail-Safe Clock Monitor (FSCM) In Sleep mode, all clock sources are disabled. Timer2/4/6/8 will not increment and the state of the module will not change. If the ECCPx pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state. If Two-Speed Start-ups are enabled, the initial start-up frequency from HF-INTOSC and the postscaler may not be stable immediately.
PIC18F97J94 FAMILY NOTES: DS30575A-page 338 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 19.0 CAPTURE/COMPARE/PWM (CCP) MODULES PIC18F97J94 family devices have seven CCP (Capture/Compare/PWM) modules, designated CCP4 through CCP10. All the modules implement standard Capture, Compare and Pulse-Width Modulation (PWM) modes. Note: Each CCP module contains a 16-bit register that can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register.
PIC18F97J94 FAMILY REGISTER 19-2: CCPTMRS1: CCP TIMER SELECT REGISTER 1 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 C7TSEL1 C7TSEL0 — C6TSEL0 — C5TSEL0 C4TSEL1 C4TSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 C7TSEL<1:0>: CCP7 Timer Selection bits 00 = CCP7 is based off of TMR1/TMR2 01 = CCP7 is based off of TMR5/TMR4 10 = CCP7 is based off of TMR5/TMR6 11 = CCP7 is base
PIC18F97J94 FAMILY REGISTER 19-3: CCPTMRS2: CCP TIMER SELECT REGISTER 2 U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — — — C10TSEL0 — C9TSEL0 C8TSEL1 C8TSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 C10TSEL0: CCP10 Timer Selection bit 0 = CCP10 is based off of TMR1/TMR2 1 = CCP10 is based off of TMR5/TMR2 bit 3 Unimplemented: Read as ‘0’
PIC18F97J94 FAMILY REGISTER 19-4: CCPRxL: CCPx PERIOD LOW BYTE REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x CCPRxL7 CCPRxL6 CCPRxL5 CCPRxL4 CCPRxL3 CCPRxL2 CCPRxL1 CCPRxL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown CCPRxL<7:0>: CCPx Period Register Low Byte bits Capture mode: Capture Register Low Byte Compare mode: Compare Register Low Byte
PIC18F97J94 FAMILY 19.1 CCP Module Configuration TABLE 19-1: Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. 19.1.1 CCP MODULES AND TIMER RESOURCES The CCP modules utilize Timers, 1 through 8, that vary with the selected mode.
PIC18F97J94 FAMILY 19.1.2 OPEN-DRAIN OUTPUT OPTION When operating in Output mode (the Compare or PWM modes), the drivers for the CCPx pins can be optionally configured as open-drain outputs. This feature allows the voltage level on the pin to be pulled to a higher level through an external pull-up resistor and allows the output to communicate with external circuits without the need for additional level shifters. The open-drain output option is controlled by the CCPxOD bits (ODCON2<7:1>).
PIC18F97J94 FAMILY FIGURE 19-1: CAPTURE MODE OPERATION BLOCK DIAGRAM TMR5H Set CCP5IF C5TSEL0 CCP5 Pin Prescaler 1, 4, 16 and Edge Detect CCP5CON<3:0> Q1:Q4 4 4 CCPR5L TMR1 Enable TMR1H TMR1L TMR3H TMR3L Set CCP4IF 4 CCP4CON<3:0> C4TSEL1 C4TSEL0 CCP4 Pin Prescaler 1, 4, 16 TMR5 Enable CCPR5H C5TSEL0 TMR5L and Edge Detect TMR3 Enable CCPR4H CCPR4L TMR1 Enable C4TSEL0 C4TSEL1 Note: 19.2.3 TMR1L This block diagram uses CCP4 and CCP5, and their appropriate timers as an example.
PIC18F97J94 FAMILY 19.3 Compare Mode 19.3.3 SOFTWARE INTERRUPT MODE In Compare mode, the 16-bit CCPR4 register value is constantly compared against the Timer register pair value selected in the CCPTMR1 register. When a match occurs, the CCP4 pin can be: When the Generate Software Interrupt mode is chosen (CCP4M<3:0> = 1010), the CCP4 pin is not affected. Only a CCP interrupt is generated, if enabled, and the CCP4IE bit is set. • • • • 19.3.
PIC18F97J94 FAMILY FIGURE 19-2: COMPARE MODE OPERATION BLOCK DIAGRAM CCPR5H Set CCP5IF CCPR5L Special Event Trigger (Timer1/5 Reset) CCP5 Pin Compare Match Comparator S Output Logic Q R TRIS Output Enable 4 CCP5CON<3:0> TMR1H TMR1L TMR5H TMR5L 0 1 C5TSEL0 0 TMR1H TMR1L 1 TMR3H TMR3L Special Event Trigger (Timer1/Timer3 Reset) C4TSEL1 C4TSEL0 Set CCP4IF Comparator CCPR4H CCPR4L Compare Match CCP4 Pin Output Logic 4 S Q R TRIS Output Enable CCP4CON<3:0> Note: This block di
PIC18F97J94 FAMILY 19.4 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCP4 pin produces up to a 10-bit resolution PWM output. Since the CCP4 pin is multiplexed with a PORTC or PORTE data latch, the appropriate TRIS bit must be cleared to make the CCP4 pin an output. Note: A PWM output (Figure 19-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
PIC18F97J94 FAMILY 19.4.2 PWM DUTY CYCLE The PWM duty cycle is specified, to use CCP4 as an example, by writing to the CCPR4L register and to the CCP4CON<5:4> bits. Up to 10-bit resolution is available. The CCPR4L contains the eight MSbs and the CCP4CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR4L:CCP4CON<5:4>.
PIC18F97J94 FAMILY NOTES: DS30575A-page 350 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 20.0 20.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D Converters, etc.
PIC18F97J94 FAMILY 20.3 SPI Mode FIGURE 20-1: The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of SPI are supported. To accomplish communication, three pins are typically used. These pins must be assigned through the PPS-Lite Configuration registers before use.
PIC18F97J94 FAMILY 20.3.1 REGISTERS Each MSSP module has four registers for SPI mode operation. These are: • • • • MSSPx Control Register 1 (SSPxCON1) MSSPx Status Register (SSPxSTAT) MSSPx Control Register 3 (SSPxCON3) Serial Receive/Transmit Buffer Register (SSPxBUF) • MSSPx Shift Register (SSPxSR) – Not directly accessible SSPxSR is the shift register used for shifting data in or out. SSPxBUF is the buffer register to which data bytes are written to or read from.
PIC18F97J94 FAMILY REGISTER 20-2: SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV(1) SSPEN(2) CKP SSPM3(4) SSPM2(4) SSPM1(4) SSPM0(4) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPxBUF register is written while it is still transmitting the previous word (must
PIC18F97J94 FAMILY REGISTER 20-3: SSPxCON3: MSSP CONTROL REGISTER 3 (SPI MODE) R/HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ACKTIM: Acknowledge Time Status bit Unused in SPI.
PIC18F97J94 FAMILY 20.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). These control bits allow the following to be specified: • I/O pins must be mapped to the SPI peripheral in order to function. See Section 11.15 “PPS-Lite” for an explanation of the PPS-Lite mapping feature.
PIC18F97J94 FAMILY 20.3.4 ENABLING SPI I/O 20.3.5 TYPICAL CONNECTION To enable the serial port, the peripheral must first be mapped to I/O pins using the PPS-Lite feature. To enable the SPI peripheral, the MSSPx Enable bit, SSPEN (SSPxCON1<5>) must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPxCON registers and then set the SSPEN bit. This configures the SDIx, SDOx, SCKx and SSx pins as serial port pins.
PIC18F97J94 FAMILY 20.3.6 MASTER MODE The master can initiate the data transfer at any time because it controls the SCKx signal. The master determines when the slave (Processor 2, Figure 20-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be disabled (programmed as an input).
PIC18F97J94 FAMILY 20.3.7 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. While in Slave mode, the external clock is supplied by the external clock source on the SCKx pin.
PIC18F97J94 FAMILY FIGURE 20-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx SDIx (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle after Q2 SSPxSR to SSPxBUF FIGURE 20-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF SDOx bit 7 SDIx (SMP = 0) bit 7 bi
PIC18F97J94 FAMILY 20.3.9 OPERATION IN POWER-MANAGED MODES In SPI Master mode, module clocks may be operating at a different speed than when in full-power mode. In the case of Sleep mode, all clocks are halted. In Idle modes, a clock is provided to the peripherals. That clock can be from the primary clock source, the secondary clock (SOSC Oscillator) or the INTOSC source. 20.3.11 Table 20-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits.
PIC18F97J94 FAMILY 20.4 SPI DMA MODULE The SPI DMA module contains control logic to allow the MSSP1 module to perform SPI Direct Memory Access transfers. This enables the module to quickly transmit or receive large amounts of data with relatively little CPU intervention. When the SPI DMA module is used, MSSP1 can directly read and write to general purpose SRAM. When the SPI DMA module is not enabled, MSSP1 functions normally, but without DMA capability.
PIC18F97J94 FAMILY 20.4.4.1 DMACON1 The DMACON1 register is used to select the main operating mode of the SPI DMA module. The SSCON1 and SSCON0 bits are used to control the slave select pin. When MSSP1 is used in SPI Master mode with the SPI DMA module, SSDMA can be controlled by the DMA module as an output pin.
PIC18F97J94 FAMILY REGISTER 20-4: DMACON1: DMA CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSCON1 SSCON0 TXINC RXINC DUPLEX1 DUPLEX0 DLYINTEN DMAEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 SSCON<1:0>: SSDMA Output Control bits (Master modes only) 11 = SSDMA is asserted for the duration of 4 bytes; DLYINTEN is always reset low 01
PIC18F97J94 FAMILY 20.4.4.2 DMACON2 The DMACON2 register contains control bits for controlling interrupt generation and inter-byte delay behavior. The INTLVL<3:0> bits are used to select when an SSP1IF interrupt should be generated. The function of the DLYCYC<3:0> bits depends on the SPI operating mode (Master/Slave), as well as the DLYINTEN setting. In SPI Master mode, the REGISTER 20-5: DLYCYC<3:0> bits can be used to control how much time the module will Idle between bytes in a transfer.
PIC18F97J94 FAMILY REGISTER 20-5: bit 3-0 DMACON2: DMA CONTROL REGISTER 2 (CONTINUED) INTLVL<3:0>: Watermark Interrupt Enable bits These bits specify the amount of remaining data yet to be transferred (transmitted and/or received) upon which an interrupt is generated.
PIC18F97J94 FAMILY 20.4.4.3 DMABCH and DMABCL The DMABCH and DMABCL register pair forms a 10-bit Byte Count register, which is used by the SPI DMA module to send/receive up to 1,024 bytes for each DMA transaction. When the DMA module is actively running (DMAEN = 1), the DMA Byte Count register decrements after each byte is transmitted/received. The DMA transaction will halt and the DMAEN bit will be automatically cleared by hardware after the last byte has completed.
PIC18F97J94 FAMILY The SPI DMA module can write received data to all general purpose memory on the device, including memory used for USB endpoint buffers. The SPI DMA module cannot be used to modify the Special Function Registers contained in Banks 14 and 15. 20.4.5 INTERRUPTS The SPI DMA module alters the behavior of the SSP1IF interrupt flag. In normal non-DMA modes, the SSP1IF is set once after every single byte is transmitted/received through the MSSP1 module.
PIC18F97J94 FAMILY 20.4.6 USING THE SPI DMA MODULE The following steps would typically be taken to enable and use the SPI DMA module: 1. 2. 3. Configure the I/O pins, which will be used by MSSP2: a) Assign SCK1, SDO1, SDI1 and SS1 to the RPn pins, as appropriate for the SPI mode which will be used. Only functions which will be used need to be assigned to a pin. b) Initialize the associated LATx registers for the desired Idle SPI bus state.
PIC18F97J94 FAMILY EXAMPLE 20-2: 512-BYTE SPI MASTER MODE INIT AND TRANSFER ;For this example, let's use RP3(RA3) for SCK1, ;RP1(RA1) for SDO1, and RP0(RA0) for SDI1 ;Let’s use SPI master mode, CKE = 0, CKP = 0, ;without using slave select signalling.
PIC18F97J94 FAMILY EXAMPLE 20-2: ; ;DestBuf ; ;SrcBuf ; 512-BYTE SPI MASTER MODE INIT AND TRANSFER (CONTINUED) udata res 0x500 0x200 res 0x200 PrepareTransfer: movlw movwf movlw movwf ;Let’s reserve 0x500-0x6FF for use as our SPI ;receive data buffer in this example ;Lets reserve 0x700-0x8FF for use as our SPI ;transmit data buffer in this example HIGH(DestBuf) RXADDRH LOW(DestBuf) RXADDRL ;Get high byte of DestBuf address (0x05) ;Load upper four bits of the RXADDR register ;Get low byte of the Des
PIC18F97J94 FAMILY 20.5 I2C Mode 20.5.1 The MSSPx module in I2C™ mode fully implements all master and slave functions (including general call support), and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSPx module implements the standard mode specifications, as well as 7-bit and 10-bit addressing.
PIC18F97J94 FAMILY REGISTER 20-6: R/W-0 SSPxSTAT: MSSPx STATUS REGISTER (I2C™ MODE) R/W-0 SMP CKE R-0 R-0 R-0 D/A (1) (1) P S R-0 R/W (2,3) R-0 R-0 UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control is disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control is enab
PIC18F97J94 FAMILY REGISTER 20-7: R/W-0 SSPxCON1: MSSPx CONTROL REGISTER 1 (I2C™ MODE) R/W-0 WCOL SSPOV R/W-0 SSPEN (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CKP SSPM3(2) SSPM2(2) SSPM1(2) SSPM0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPxBUF register was attempted while the I2C con
PIC18F97J94 FAMILY REGISTER 20-8: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ MASTER MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit Unused in Master mode.
PIC18F97J94 FAMILY REGISTER 20-9: SSPxCON3: MSSP CONTROL REGISTER 3 (I2C MASTER MODE) R/HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ACKTIM: Acknowledge Time Status bit Unused in Master mode.
PIC18F97J94 FAMILY REGISTER 20-10: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ SLAVE MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(1) RCEN(1) PEN(1) RSEN(1) SEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit 1 = Enables interrupt when a general call address (0000h) is received in the SSPxSR 0 = G
PIC18F97J94 FAMILY REGISTER 20-11: SSPxCON3: MSSP CONTROL REGISTER 3 (I2C SLAVE MODE) R/HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ACKTIM: Acknowledge Time Status bit 1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCL clock 0 =
PIC18F97J94 FAMILY REGISTER 20-12: SSPxMSK: MSSPx I2C™ SLAVE ADDRESS MASK REGISTER (7-BIT MASKING MODE)(1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown MSK<7:0>: Slave Address Mask Select bits 1 = Masking of corresponding bit of SSPxADD is enabled 0 = Masking of corre
PIC18F97J94 FAMILY 20.5.2 OPERATION The MSSPx module functions are enabled by setting the MSSPx Enable bit, SSPEN (SSPxCON1<5>). The SSPxCON1 register allows control of the I2C operation.
PIC18F97J94 FAMILY 20.5.4.1 Address Masking Modes Masking an address bit causes that bit to become a “don’t care”. When one address bit is masked, two addresses will be Acknowledged and cause an interrupt. It is possible to mask more than one address bit at a time, which greatly expands the number of addresses Acknowledged. The I2C slave behaves the same way, whether address masking is used or not.
PIC18F97J94 FAMILY 20.5.4.3 7-Bit Address Masking Mode Unlike 5-bit masking, 7-Bit Address Masking mode uses a mask of up to 8 bits (in 10-bit addressing) to define a range of addresses that can be Acknowledged, using the lowest bits of the incoming address. This allows the module to Acknowledge up to 127 different addresses with 7-bit addressing, or 255 with 10-bit addressing (see Example 20-4).
PIC18F97J94 FAMILY 20.5.5 RECEPTION When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and the SDAx line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined if either bit, BF (SSPxSTAT<0>), is set or bit, SSPOV (SSPxCON1<6>), is set.
DS30575A-page 384 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 (CKP does not reset to ‘0’ when SEN = 0) CKP (SSPxCON<4>) SSPOV (SSPxCON1<6>) BF (SSPxSTAT<0>) SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S A7 7 A1 8 9 ACK R/W = 0 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPxBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPxBUF is still full.
2012 Microchip Technology Inc. 2 A6 3 A5 4 X 5 A3 6 X 7 X 8 9 ACK R/W = 0 1 D7 3 D5 4 D4 Cleared in software SSPxBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2: In this example, an address equal to A7.A6.A5.X.A3.X.X will be Acknowledged and cause 5 D3 Receiving Data Note 1: x = Don’t care (i.e., address bit can either be a ‘1’ or a ‘0’).
DS30575A-page 386 2 Data in sampled 1 A6 CKP (SSPxCON<4>) BF (SSPxSTAT<0>) SSPxIF (PIR1<3> or PIR3<7>) S A7 3 4 A4 5 A3 6 A2 Receiving Address A5 7 A1 8 R/W = 1 9 ACK 2 D6 3 D5 4 5 D3 6 D2 7 8 D1 D0 Transmitting Data D4 9 ACK CKP is set in software Cleared in software From SSPxIF ISR SSPxBUF is written in software Clear by reading SCLx held low while CPU responds to SSPxIF 1 D7 1 D7 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 ACK CKP is set in software Clear
2012 Microchip Technology Inc.
DS30575A-page 388 2 1 3 1 4 1 5 0 7 A8 8 UA is set indicating that the SSPxADD needs to be updated SSPxBUF is written with contents of SSPxSR 6 A9 9 (CKP does not reset to ‘0’ when SEN = 0) CKP (SSPxCON<4>) UA (SSPxSTAT<1>) SSPOV (SSPxCON1<6>) BF (SSPxSTAT<0>) Cleared in software SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S 1 ACK R/W = 0 A7 2 4 A4 5 A3 6 A2 8 9 A0 ACK UA is set indicating that SSPxADD needs to be updated Cleared by hardware when SSPxADD is updated with low b
2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 20.5.7 CLOCK STRETCHING Both 7-Bit and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPxCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCLx pin to be held low at the end of each data receive sequence. 20.5.7.
PIC18F97J94 FAMILY 20.5.7.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCLx output is forced to ‘0’. However, clearing the CKP bit will not assert the SCLx output low until the SCLx output is already sampled low. Therefore, the CKP bit will not assert the FIGURE 20-14: SCLx line until an external I2C master device has already asserted the SCLx line. The SCLx output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCLx.
DS30575A-page 392 2 A6 CKP (SSPxCON<4>) SSPOV (SSPxCON1<6>) BF (SSPxSTAT<0>) SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S A7 3 4 A4 5 A3 6 A2 Receiving Address A5 7 A1 8 9 ACK R/W = 0 3 4 D4 5 D3 Receiving Data D5 Cleared in software 2 D6 If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to ‘0’ and no clock stretching will occur SSPxBUF is read 1 D7 6 D2 7 D1 9 ACK 1 D7 BF is set after falling edge of the 9th clock, CKP is reset to ‘0’ a
2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 20.5.8 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPxSR is transferred to the SSPxBUF, the BF flag bit is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), the SSPxIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices.
PIC18F97J94 FAMILY MASTER MODE 5. Master mode is enabled by setting and clearing the appropriate SSPMx bits in SSPxCON1, and by setting the SSPEN bit. In Master mode, the SCLx and SDAx lines are manipulated by the MSSPx hardware if the TRIS bits are set. Generate an Acknowledge condition at the end of a received byte of data. Generate a Stop condition on SDAx and SCLx. 6. Note: The Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions.
PIC18F97J94 FAMILY 20.5.9.1 I2C™ Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDAx while SCLx outputs the serial clock.
PIC18F97J94 FAMILY 20.5.10 BAUD RATE 20.5.10.1 I2C In Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPxADD register (Figure 20-19). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to 0 and stops until another reload has taken place. The BRG count is decremented, twice per instruction cycle (TCY), on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically.
PIC18F97J94 FAMILY 20.5.10.2 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCLx pin (SCLx allowed to float high). When the SCLx pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the FIGURE 20-20: SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and begins counting.
PIC18F97J94 FAMILY 20.5.11 I2C™ MASTER MODE START CONDITION TIMING Note: To initiate a Start condition, the user sets the Start Enable bit, SEN (SSPxCON2<0>). If the SDAx and SCLx pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and starts its count. If SCLx and SDAx are both sampled high when the Baud Rate Generator times out (TBRG), the SDAx pin is driven low.
PIC18F97J94 FAMILY 20.5.12 I2C™ MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit (SSPxCON2<1>) is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCLx pin is asserted low. When the SCLx pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPxADD<5:0> and begins counting.
PIC18F97J94 FAMILY 20.5.13 I2C™ MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address, is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is asserted (see data hold time specification Parameter 106).
DS30575A-page 402 S R/W PEN SEN BF (SSPxSTAT<0>) SSPxIF SCLx SDAx A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 After Start condition, SEN cleared by hardware SSPxBUF written 1 9 D7 1 SCLx held low while CPU responds to SSPxIF ACK = 0 R/W = 0 SSPxBUF written with 7-bit address and R/W, start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPxBUF is written in software Cleared in software service routine from MSSPx interrupt 2 D6 Tran
2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 20.5.15 ACKNOWLEDGE SEQUENCE TIMING 20.5.16 A Stop bit is asserted on the SDAx pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPxCON2<2>). At the end of a receive/ transmit, the SCLx line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDAx line low. When the SDAx line is sampled low, the Baud Rate Generator is reloaded and counts down to 0.
PIC18F97J94 FAMILY 20.5.17 SLEEP OPERATION 20.5.20 I2C While in Sleep mode, the module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSPx interrupt is enabled). 20.5.18 EFFECTS OF A RESET A Reset disables the MSSPx module and terminates the current transfer. 20.5.
PIC18F97J94 FAMILY 20.5.20.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDAx or SCLx is sampled low at the beginning of the Start condition (Figure 20-28). SCLx is sampled low before SDAx is asserted low (Figure 20-29). During a Start condition, both the SDAx and the SCLx pins are monitored. If the SDAx pin is sampled low during this count, the BRG is reset and the SDAx line is asserted early (Figure 20-30).
PIC18F97J94 FAMILY FIGURE 20-29: BUS COLLISION DURING START CONDITION (SCLx = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, Enable Start Sequence if SDAx = 1, SCLx = 1 SCLx SCLx = 0 Before SDAx = 0, Bus Collision Occurs, Set BCLxIF SEN SCLx = 0 Before BRG Time-out, Bus Collision Occurs, Set BCLxIF BCLxIF Interrupt Cleared in Software S ‘0’ ‘0’ SSPxIF ‘0’ ‘0’ FIGURE 20-30: BRG RESET DUE TO SDAx ARBITRATION DURING START CONDITION SDAx = 0, SCLx = 1 Set S Less than TBRG SDAx Set SSPxIF TBRG S
PIC18F97J94 FAMILY 20.5.20.2 Bus Collision During a Repeated Start Condition If SDAx is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 20-31). If SDAx is sampled high, the BRG is reloaded and begins counting. If SDAx goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDAx at exactly the same time.
PIC18F97J94 FAMILY 20.5.20.3 Bus Collision During a Stop Condition The Stop condition begins with SDAx asserted low. When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD<6:0> and counts down to 0. After the BRG times out, SDAx is sampled. If SDAx is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 20-33).
PIC18F97J94 FAMILY NOTES: DS30575A-page 410 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 21.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of four serial I/O modules. (Generically, the EUSART is also known as a Serial Communications Interface or SCI.) The EUSART can be configured as a full-duplex, asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers.
PIC18F97J94 FAMILY REGISTER 21-1: TXSTAx: EUSARTx TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care.
PIC18F97J94 FAMILY REGISTER 21-2: RCSTAx: EUSARTx RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port is enabled 0 = Serial port is disabled (held in Reset) bit 6 RX9: 9-Bit Receive Enable bit 1 = Sele
PIC18F97J94 FAMILY REGISTER 21-3: BAUDCONx: BAUD RATE CONTROL REGISTER x R/W-0 R-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ABDOVF RCIDL RXDTP TXCKP BRG16 IREN WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 =
PIC18F97J94 FAMILY bit 0 Note 1: ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enables baud rate measurement on the next character, requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement is disabled or has completed Synchronous mode: Unused in this mode. This feature is only available in Asynchronous mode with the 16x clock preset. The 16x clock is present for both the x16 and x64 BRG configurations. 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 21.1 Baud Rate Generator (BRG) The BRG is a dedicated, 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSARTx. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>) selects 16-bit mode. The SPBRGHx:SPBRGx register pair controls the period of a free-running timer. In Asynchronous mode, bits, BRGH (TXSTAx<2>) and BRG16 (BAUDCONx<3>), also control the baud rate. In Synchronous mode, BRGH is ignored.
PIC18F97J94 FAMILY TABLE 21-2: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error (decimal) % Error — — — — — — — — 1.221 1.73 255 1.202 2.441 1.73 255 9.615 0.16 64 2.404 0.16 129 9.766 1.73 31 19.2 19.531 1.73 31 19.531 1.73 57.6 56.818 -1.36 10 62.500 115.2 125.000 8.51 4 104.167 % Error 0.3 — — 1.2 — 2.4 9.6 SPBRG value SPBRG value FOSC = 10.
PIC18F97J94 FAMILY TABLE 21-2: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) % Error FOSC = 20.000 MHz SPBRG value (decimal) Actual Rate (K) % Error SPBRG value FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error FOSC = 8.000 MHz SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1.2 1.200 0.02 2082 1.200 -0.
PIC18F97J94 FAMILY 21.1.3 AUTO-BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source.
PIC18F97J94 FAMILY FIGURE 21-1: BRG Value AUTOMATIC BAUD RATE CALCULATION XXXXh RXx Pin 0000h 001Ch Start Edge #1 Bit 1 Bit 0 Edge #2 Bit 3 Bit 2 Edge #3 Bit 5 Bit 4 Edge #4 Bit 7 Bit 6 Edge #5 Stop Bit BRG Clock Auto-Cleared Set by User ABDEN bit RCxIF bit (Interrupt) Read RCREGx SPBRGx XXXXh 1Ch SPBRGHx XXXXh 00h Note: The ABD sequence requires the EUSARTx module to be configured in Asynchronous mode and WUE = 0.
PIC18F97J94 FAMILY 21.2 EUSARTx Asynchronous Mode Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx register is empty and the TXxIF flag bit is set. This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXxIE. TXxIF will be set regardless of the state of TXxIE; it cannot be cleared in software.
PIC18F97J94 FAMILY FIGURE 21-4: Write to TXREGx BRG Output (Shift Clock) ASYNCHRONOUS TRANSMISSION Word 1 TXx (pin) Start bit FIGURE 21-5: bit 1 bit 7/8 Stop bit Word 1 TXxIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) bit 0 1 TCY Word 1 Transmit Shift Reg ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREGx Word 1 Word 2 BRG Output (Shift Clock) TXx (pin) TXxIF bit (Interrupt Reg. Flag) TRMT bit (Transmit Shift Reg.
PIC18F97J94 FAMILY 21.2.2 EUSARTx ASYNCHRONOUS RECEIVER 21.2.3 The receiver block diagram is shown in Figure 21-6. The data is received on the RXx pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems.
PIC18F97J94 FAMILY FIGURE 21-7: RXx (pin) ASYNCHRONOUS RECEPTION Start bit bit 0 bit 1 bit 7/8 Stop bit Rcv Shift Reg Rcv Buffer Reg Read Rcv Buffer Reg RCREGx Start bit bit 0 bit 7/8 Stop bit Start bit bit 7/8 Stop bit Word 2 RCREGx Word 1 RCREGx RCxIF (Interrupt Flag) OERR bit CREN Note: 21.2.4 This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word, causing the OERR (Overrun) bit to be set.
PIC18F97J94 FAMILY 21.2.4.2 Special Considerations Using the WUE Bit The timing of WUE and RCxIF events may cause some confusion when it comes to determining the validity of received data. As noted, setting the WUE bit places the EUSARTx in an Idle mode. The wake-up event causes a receive interrupt by setting the RCxIF bit. The WUE bit is cleared after this when a rising edge is seen on RXx/DTx. The interrupt condition is then cleared by reading the RCREGx register.
PIC18F97J94 FAMILY 21.2.5 BREAK CHARACTER SEQUENCE The EUSARTx module has the capability of sending the special Break character sequences that are required by the LIN/J2602 bus standard. The Break character transmit consists of a Start bit, followed by twelve ‘0’ bits and a Stop bit. The Frame Break character is sent whenever the SENDB and TXEN bits (TXSTAx<3> and TXSTAx<5>, respectively) are set while the Transmit Shift Register is loaded with data.
PIC18F97J94 FAMILY 21.3 EUSARTx Synchronous Master Mode The Synchronous Master mode is entered by setting the CSRC bit (TXSTAx<7>). In this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit, SYNC (TXSTAx<4>).
PIC18F97J94 FAMILY FIGURE 21-11: SYNCHRONOUS TRANSMISSION Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 RX1/DT1 Pin bit 0 bit 1 bit 2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 bit 7 bit 0 TX1/CK1 Pin (TXCKP = 0) bit 1 bit 7 Word 2 Word 1 TX1/CK1 Pin (TXCKP = 1) Write to TxREG1 Reg Write Word 1 Write Word 2 Tx1IF bit (Interrupt Flag) TRMT bit TXEN bit Note: ‘1’ ‘1’ Sync Master mode, SPBRGx = 0, continuous transmission of two 8-bit words.
PIC18F97J94 FAMILY 21.3.2 EUSARTx SYNCHRONOUS MASTER RECEPTION 3. 4. 5. 6. Ensure bits, CREN and SREN, are clear. If interrupts are desired, set enable bit, RCxIE. If 9-bit reception is desired, set bit, RX9. If a single reception is required, set bit, SREN. For continuous reception, set bit, CREN. 7. Interrupt flag bit, RCxIF, will be set when reception is complete and an interrupt will be generated if the enable bit, RCxIE, was set. 8.
PIC18F97J94 FAMILY 21.4 EUSARTx Synchronous Slave Mode Synchronous Slave mode is entered by clearing bit, CSRC (TXSTAx<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CKx pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 21.4.
PIC18F97J94 FAMILY 21.5 Infrared Support 21.5.1.1 This module provides support for two types of infrared USART port implementations: • IrDA clock output to support an external IrDA encoder/decoder device • Full implementation of the IrDa encoder and decoder as part of the USART logic Since the 16x clock is required to perform the IrDA encoding, both by this module and the external transmitter, this feature only works in the 16x Baud Rate mode and is not available in the 4x mode. 21.5.
PIC18F97J94 FAMILY 21.5.2 BUILT-IN IrDA ENCODER AND DECODER The built-in IrDA encoder and decoder functionality is enabled using the IREN bit in the BAUDCONx register while the module is in Asynchronous mode (SYNC = 0). When enabled (IREN = 1), the Receive pin (RXx) acts as the input from the infrared receiver. The Transmit pin (TXx) acts as the output to the infrared transmitter. The 16x clock must be available for this feature to work properly.
PIC18F97J94 FAMILY 21.5.2.3 IrDA Decoder Function 21.5.2.4 The decoder works by taking the serial data from the RXx pin and replacing it with the decoded data stream. The stream is decoded based on falling edge detection of the RXx input. Each falling edge of RXx causes the decoded data to be driven low for 16 periods of the 16x Baud Clock. If another falling edge has been detected by the time the 16 periods expire, the decoded data remains low for another 16 periods.
PIC18F97J94 FAMILY NOTES: DS30575A-page 434 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 22.
PIC18F97J94 FAMILY FIGURE 22-1: 12-BIT A/D CONVERTER BLOCK DIAGRAM (PIC18F97J94 FAMILY) Internal Data Bus AVDD VR Select AVSS VREF+ VREF- VR+ 16 VR- VBG Comparator VINH VINL AN0 VRS/H VR+ DAC AN1 12-Bit SAR AN2 Conversion Logic AN3 Data Formatting AN4 VINH AN5 ADC1BUF0: ADC1BUFn(3) MUX A AN6 AN7 AN8 AD1CON1 VINL AN9 AD1CON2 AD1CON3 AD1CON4 AD1CON5 AD1CHS AD1CHITL AD1CHITH MUX B AN(n-1) ANn(1) VBG(2) VINH AD1CSSL AD1CSSH AD1CTMENL AD1CTMENH AD1DMBUF VINL VBG/2(2) VBG/6(2) VDDCORE
PIC18F97J94 FAMILY 22.1 Registers The 12-bit A/D converter module uses up to 75 registers for its operation. All registers are mapped in the data memory space. 22.1.
PIC18F97J94 FAMILY REGISTER 22-1: ANCON1: ANALOG SELECT CONTROL REGISTER 1 (FOR AN7-AN0) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ANSEL7: Pin RG0 Analog Enable bit 1 = Pin configured as an analog channel – digital input is disabled and reads ‘0’ 0 = P
PIC18F97J94 FAMILY REGISTER 22-2: ANCON2: ANALOG SELECT CONTROL REGISTER 2 (FOR AN15-AN8) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANSEL15 ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 ANSEL8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ANSEL15: Pin RG4 Analog Enable bit 1 = Pin configured as an analog channel – digital input is disabled and reads ‘
PIC18F97J94 FAMILY REGISTER 22-3: ANCON3: ANALOG SELECT CONTROL REGISTER 3 (FOR AN23-AN16) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANSEL23 ANSEL22 ANSEL21 ANSEL20 ANSEL19 ANSEL18 ANSEL17 ANSEL16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ANSEL23: Pin RH7 Analog Enable 1 = Pin configured as an analog channel – digital input disabled and reads ‘0’ 0
PIC18F97J94 FAMILY REGISTER 22-4: ADCON1H: A/D CONTROL REGISTER 1 HIGH R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 ADON — — — — MODE12 FORM1 FORM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADON: A/D Operating Mode bit 1 = A/D Converter module is operating 0 = A/D Converter is off bit 6-3 Unimplemented: Read as ‘0’ bit 2 MODE12: 12-Bit Operation Mode bit 1 = 12-bit A/D opera
PIC18F97J94 FAMILY REGISTER 22-5: ADCON1L: A/D CONTROL REGISTER 1 LOW R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0, HSC R/C-0, HSC SSRC3 SSRC2 SSRC1 SSRC0 — ASAM SAMP DONE bit 7 bit 0 Legend: C = Clearable bit U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 SSRC<3:0>: Sample Clock Source Select bits 1xxx = Unimplemented, do not use 0111 = The
PIC18F97J94 FAMILY REGISTER 22-6: ADCON2H: A/D CONTROL REGISTER 2 HIGH R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 PVCFG1 PVCFG0 NVCFG0 OFFCAL BUFREGEN CSCNA — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 PVCFG<1:0>: Converter Positive Voltage Reference Configuration bits 1x = Unimplemented, do not use 01 = External VREF+ 00 = AVDD bit 5 NVCFG0: Conve
PIC18F97J94 FAMILY REGISTER 22-7: ADCON2L: A/D CONTROL REGISTER 2 LOW R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS(1) SMPI4 SMPI3 SMPI2 SMPI1 SMPI0 BUFM(1) ALTS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 BUFS: Buffer Fill Status bit(1) 1 = A/D is filling the upper half of the buffer; user should access data in the lower half 0 = A/D is filling the
PIC18F97J94 FAMILY REGISTER 22-8: ADCON3H: A/D CONTROL REGISTER 3 HIGH R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC EXTSAM PUMPEN SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADRC: A/D Conversion Clock Source bit 1 = RC Clock 0 = Clock derived from system clock bit 6 EXTSAM: Extended Sampling Time bit 1 = A/D is still sampling after SAMP =
PIC18F97J94 FAMILY REGISTER 22-10: ADCON5H: A/D CONTROL REGISTER 5 HIGH R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 ASENA LPENA CTMUREQ — — — ASINTMD1 ASINTMD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ASENA: Auto-Scan Enable bit 1 = Auto-scan is enabled 0 = Auto-scan is disabled bit 6 LPENA: Low-Power Enable bit 1 = Low power is enabled after scan 0 = Ful
PIC18F97J94 FAMILY REGISTER 22-11: ADCON5L: A/D CONTROL REGISTER 5 LOW U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — WM1 WM0 CM1 CM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 WM<1:0>: Write Mode bits 11 = Reserved 10 = Auto-compare only (conversion results are not saved, but interrupts are generated when a valid mat
PIC18F97J94 FAMILY REGISTER 22-12: ADCHS0H: A/D SAMPLE SELECT REGISTER 0 HIGH R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NB2 CH0NB1 CH0NB0 CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 CH0NB<2:0>: Sample B Channel 0 Negative Input Select bits 1xx = Unimplemented 011 = Unimplemented 010 = AN1 001 = Unimplemented 000
PIC18F97J94 FAMILY REGISTER 22-13: ADCHS0L: A/D SAMPLE SELECT REGISTER 0 LOW R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA2 CH0NA1 CH0NA0 CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 CH0NA<2:0>: Sample A Channel 0 Negative Input Select bits 1xx = Unimplemented 011 = Unimplemented 010 = AN1 001 = Unimplemented 000 =
PIC18F97J94 FAMILY REGISTER 22-14: ADHIT1H: A/D SCAN COMPARE HIT REGISTER 1 HIGH (HIGH WORD) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CHH30 CHH29 CHH28 CHH27 CHH26 CHH25 CHH24 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-0 CHH<30:24>: A/D Compare Hit bits If CM<1:0> = 11: 1 = A/D Result Buffer n has been written with
PIC18F97J94 FAMILY REGISTER 22-16: ADHIT0H: A/D SCAN COMPARE HIT REGISTER 0 HIGH (HIGH WORD) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHH15 CHH14 CHH13 CHH12 CHH11 CHH10 CHH9 CHH8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown CHH<15:8>: A/D Compare Hit bits If CM<1:0> = 11: 1 = A/D Result Buffer n has been written with data or a match has occurred 0 =
PIC18F97J94 FAMILY REGISTER 22-18: ADCSS1H: A/D INPUT SCAN SELECT REGISTER 1 HIGH (HIGH WORD) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CSS30 CSS29 CSS28 CSS27 CSS26 CSS25 CSS24 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-0 CSS<30:24>: A/D Input Scan Selection bits 1 = Includes corresponding channel for input scan 0 = Skips channel for i
PIC18F97J94 FAMILY REGISTER 22-20: ADCSS0H: A/D INPUT SCAN SELECT REGISTER 0 HIGH (HIGH WORD) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown CSS<15:8>: A/D Input Scan Selection bits 1 = Includes corresponding channel for input scan 0 = Skips channel for input scan R
PIC18F97J94 FAMILY REGISTER 22-22: ADCTMUEN1H: CTMU ENABLE REGISTER 1 HIGH (HIGH WORD)(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CTMUEN30 CTMUEN29 CTMUEN28 CTMUEN27 CTMUEN26 CTMUEN25 CTMUEN24 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-0 CTMUEN<30:24>: CTMU Enabled During Conversion bits 1 = CTMU is enabled and c
PIC18F97J94 FAMILY REGISTER 22-24: ADCTMUEN0H: CTMU ENABLE REGISTER 0 HIGH (HIGH WORD)(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMUEN15 CTMUEN14 CTMUEN13 CTMUEN12 CTMUEN11 CTMUEN10 CTMUEN9 CTMUEN8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: x = Bit is unknown CTMUEN<15:8>: CTMU Enabled During Conversion bits 1 = CTMU is enabled and connected to the select
PIC18F97J94 FAMILY 22.2 A/D Terminology and Conversion Sequence Sample time is the time that the A/D module's S/H amplifier is connected to the analog input pin. The sample time may be started and ended automatically by the A/D Converter's hardware or under direct program control. There is a minimum sample time to ensure that the S/H amplifier will give sufficient accuracy for the A/D conversion. The conversion trigger ends the sampling time and begins an A/D conversion or a repeating sequence.
PIC18F97J94 FAMILY 22.2.1 OPERATION AS A STATE MACHINE The A/D conversion process can be thought of in terms of a finite state machine (Figure 22-3). The sample state represents the time that the input channel is connected to the S/H amplifier and the signal is passed to the converter input. The convert state is transitory. The module enters this state as soon as it exits the sample state and transitions to a different state when that is done.
PIC18F97J94 FAMILY 22.3 A/D Module Configuration All of the registers described in the previous section must be configured for module operation to be fully defined. An effective approach is first, to describe the signals and sequences for the particular application. Typically, it is an iterative process to assign signals to TABLE 22-1: port pins, to establish timing methods and to organize a scanning scheme, as well as to integrate the whole process with the software design.
PIC18F97J94 FAMILY 22.3.3 SELECTING THE A/D CONVERSION CLOCK The A/D Converter has a maximum rate at which conversions may be completed. An analog module clock, TAD, controls the conversion timing. The A/D conversion requires 14 clock periods (14 TAD) for a 12-bit conversion and 12 clock periods (12 TAD) for a 10-bit conversion. The A/D clock is derived from the device instruction clock. The period of the A/D conversion clock is software selected using a 6-bit counter.
PIC18F97J94 FAMILY The CTMU input is selected by the ADCTMUEN1H/L, ADCTMUEN0H/L registers. Setting a particular bit in one of these registers effectively assigns the analog output from the CTMU to the corresponding A/D input channel, automatically enabling the CTMU. Many devices will already have a CH0SAx bit combination designated for use of the CTMU. This setting disconnects the converter from any other load. This channel should be the one selected by the appropriate ADCTMUEN bit.
PIC18F97J94 FAMILY Conversion data stored in the ADCBUF registers will also be maintained, including any threshold values stored by the user. It may be necessary to re-initialize these registers to their proper values before re-enabling the module. When enabling the module by setting the ADON bit, the user must wait for the analog stages to stabilize. For the stabilization time, refer to Section 31.0 “Electrical Characteristics”. 22.4 22.4.
PIC18F97J94 FAMILY FIGURE 22-4: CONVERTING ONE CHANNEL, MANUAL SAMPLE START, MANUAL CONVERSION START A/D CLK TSAMP TCONV SAMP DONE ADC1BUF0 Instruction Execution BSF AD1CON1, SAMP EXAMPLE 22-1: BCF AD1CON1, SAMP CONVERTING ONE CHANNEL, MANUAL SAMPLE START, MANUAL CONVERSION START CODE int ADCValue; ANSB = 0x0001; AD1CON1 = 0x0000; AD1CHS = 0x0002; // // // // AD1CSSL = 0; AD1CON3 = 0x0002; AD1CON2 = 0; AD1CON1bits.
PIC18F97J94 FAMILY 22.5.2 CLOCKED CONVERSION TRIGGER When ADRC = 1, the conversion trigger is under A/D clock control. The SAMCx bits (ADCON3H<4:0>) select the number of TAD clock cycles between the start of sampling and the start of conversion. After the start of sampling, the module will count a number of TAD clocks specified by the SAMCx bits. The SAMCx bits must always be programmed for at least one clock cycle to ensure sampling requirements are met.
PIC18F97J94 FAMILY 22.5.2.1 Free-running Sample Conversion Sequence Using the Auto-Convert Conversion Trigger mode (SSRC<3:0> = 0111), in combination with the Auto-Sample Start mode (ASAM = 1), allows the A/D module to schedule sample/conversion sequences with no intervention by the user or other device resources. This “Clocked” mode, shown in Figure 22-7, allows continuous data collection after module initialization.
PIC18F97J94 FAMILY 22.5.3.4 Sample Time Considerations For Automatic Sampling/conversion Sequences sampling time satisfies the sampling requirements, as outlined in Section 22.9 “A/D Sampling Requirements”. Different sample/conversion sequences provide different available sampling times for the S/H channel to acquire the analog signal.
PIC18F97J94 FAMILY 22.5.4 MONITORING SAMPLE/CONVERSION STATUS The DONE bit (ADCON1L<0>) indicates the conversion state of the A/D. Generally, when the SAMP bit clears, indicating the end of sampling, the DONE bit is automatically cleared to indicate the start of conversion. If SAMP is '0' while DONE is '1', the A/D is in an inactive state. In some operational modes, the SAMP bit may also invoke and terminate sampling. In these modes, the DONE bit cannot be used to terminate conversions in progress. 22.5.
PIC18F97J94 FAMILY The BUFM bit (ADCON2L<1>) controls how the buffer is filled. When BUFM is '1', the buffer is split into two equal halves: a lower half (ADCBUF0 through ADCBUF[(n/2) - 1]) and an upper half (ADCBUF[n/2] through ADCBUFn), where n is the number of available analog channels (both internal and external). The buffers will alternately receive the conversion results after each interrupt event. The initial buffer used after BUFM is set is the lower group.
PIC18F97J94 FAMILY TABLE 22-2: NUMERICAL EQUIVALENTS OF VARIOUS RESULT CODES: 12-BIT INTEGER FORMATS 12-Bit Output Code VIN/VREF 16-Bit Integer Format/ Equivalent Decimal Value 16-Bit Signed Integer Format/ Equivalent Decimal Value 4095/4096 1111 1111 1111 0000 1111 1111 1111 4095 0000 0111 1111 1111 2047 4094/4096 1111 1111 1110 0000 1111 1111 1110 4094 0000 0111 1111 1110 2046 1 2049/4096 1000 0000 0001 0000 1000 0000 0001 2049 0000 0000 0000 0001 2048/4096 1000 0000 0000 0000
PIC18F97J94 FAMILY TABLE 22-4: VIN/VREF NUMERICAL EQUIVALENTS OF VARIOUS RESULT CODES: 10-BIT INTEGER FORMATS 10-Bit Output Code 16-Bit Integer Format/ Equivalent Decimal Value 16-Bit Signed Integer Format/ Equivalent Decimal Value 1023/1024 11 1111 1111 0000 0011 1111 1111 1023 0000 0001 1111 1111 511 1022/1024 11 1111 1110 0000 0011 1111 1110 1022 0000 0001 1111 1110 510 513/1024 10 0000 0001 0000 0010 0000 0001 513 0000 0000 0000 0001 1 512/1024 10 0000 0000 0000 0010 0000 0000 5
PIC18F97J94 FAMILY The LPENA bit (ADCON5H<6>) allows Threshold Detect to function with a low-power feature. By design, Threshold Detect can perform comparison operations when the device is in Sleep or Idle modes, waking the CPU when it generates an interrupt. Setting LPENA configures the device to return to low-power operation after the interrupt has been serviced. The Compare Mode bits, CM<1:0> (ADCON5L<1:0>), select the type of comparison to be performed.
PIC18F97J94 FAMILY 22.7.4 THRESHOLD DETECT INTERRUPTS The A/D module can generate an interrupt and set the ADIF flag based on Threshold Detect operation. This is based on completion of a Threshold Detect sequence and/or the occurrence of a valid comparison. When Threshold Detect is enabled (ASENA = 1), A/D module interrupt generation is governed by the ASINTMDx bits (ADCON5H<1:0>), superseding any configuration implemented by the SMPIx bits (ADCON2L<6:2>).
PIC18F97J94 FAMILY FIGURE 22-12: SIMPLE COMPARISON OPERATIONS (GREATER THAN AND LESS THAN) Before Conversion and Comparison ADC1BUF15 — ADC1BUF14 — ADC1BUF13 — After Conversion and Comparison Compare Only (‘10’) Compare and Store (‘01’) ADC1BUF15 — — — ADC1BUF14 — — — ADC1BUF13 — — — ADC1BUF12 — — — ADC1BUF11 — — — ADC1BUF10 — — ADC1BUF7 — ADC1BUF9 — — ADC1BUF6 — ADC1BUF8 — — — ADC1BUF7 — — — ADC1BUF6 — — — ADC1BUF5 — — Threshold Value ADC1BUF4 — —
PIC18F97J94 FAMILY FIGURE 22-13: INSIDE WINDOW COMPARISON OPERATION Before Conversion and Comparison ADC1BUF15 — ADC1BUF14 — ADC1BUF13 — ADC1BUF12 — ADC1BUF11 After Conversion and Comparison Compare Only (‘10’) Compare and Store (‘01’) ADC1BUF15 — — ADC1BUF14 — — — ADC1BUF13 — — ADC1BUF10 Threshold 2 ADC1BUF12 — — ADC1BUF9 — ADC1BUF11 — — ADC1BUF8 — ADC1BUF10 Threshold 2 Threshold 2 ADC1BUF7 — ADC1BUF9 — — ADC1BUF6 — ADC1BUF8 — — ADC1BUF5 — ADC1BUF7 — — A
PIC18F97J94 FAMILY For this reason, users must always carefully consider the allocation and use of the upper analog channels (both external and internal) when using Windowed Compare modes. Wherever possible, exclude the upper analog channels for Threshold Detect operations, and convert and test those channels in a separate routine.
PIC18F97J94 FAMILY FIGURE 22-15: OUTSIDE WINDOW COMPARISON OPERATION (UNDER THRESHOLD 1) Before Conversion and Comparison ADC1BUF15 — ADC1BUF14 — ADC1BUF13 — ADC1BUF12 — ADC1BUF11 After Conversion and Comparison Compare Only (‘10’) Compare and Store (‘01’) ADC1BUF15 — — ADC1BUF14 — — — ADC1BUF13 — — ADC1BUF10 Threshold 2 ADC1BUF12 — — ADC1BUF9 — ADC1BUF11 — — ADC1BUF8 — ADC1BUF10 Threshold 2 Threshold 2 ADC1BUF7 — ADC1BUF9 — — ADC1BUF6 — ADC1BUF8 — — ADC1BUF5
PIC18F97J94 FAMILY EXAMPLE 22-3: A/D INITIALIZATION CODE EXAMPLE ADCON1H = 0x22; // Configure sample clock source ADCON1L = 0x00; // and conversion trigger mode. // Unsigned Fraction format (FORM<1:0>=10), // Manual conversion trigger (SSRC<3:0>=0000), // Manual start of sampling (ASAM=0), // No operation in Idle mode (ADSIDL=1), // S/H in Sample (SAMP = 1) ADCON2H = 0; // Configure A/D voltage reference ADCON2L = 0; // and buffer fill modes.
PIC18F97J94 FAMILY 22.8.2 CONVERSION SEQUENCE EXAMPLES 22.8.2.1 The following configuration examples show the A/D operation in different sampling and buffering configurations. In each example, setting the ASAM bit starts automatic sampling. A conversion trigger ends sampling and starts conversion. Sampling and Converting a Single Channel Multiple Times In this case Figure 22-16, one A/D input, AN0, will be sampled and converted. The results are stored in the ADCBUFn buffer.
PIC18F97J94 FAMILY EXAMPLE 22-4: CONVERTING A SINGLE CHANNEL 16 TIMES PER INTERRUPT A/D Configuration: • • • • • • Select AN0 for S/H+ Input (CH0SA<4:0> = 00000) Select VR- for S/H- Input (CH0NA<2:0> = 000) Configure for No Input Scan (CSCNA = 0) Use Only MUX A for Sampling (ALTS = 0) Set AD1IF on Every 16th Sample (SMPI<4:0> = 01111) Configure Buffers for Single, 16-Word Results (BUFM = 0) Operational Sequence: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18.
PIC18F97J94 FAMILY 22.8.2.2 A/D Conversions While Scanning Through All Analog Inputs Other conditions are similar to those located in Section Section 22.8.2.1 “Sampling and Converting a Single Channel Multiple Times”. Figure 22-17 and Example 22-5 illustrate a typical setup, where all available analog input channels are sampled and converted. In this instance, 16 analog inputs are assumed. The set CSCNA bit specifies scanning of the A/D inputs to the S/H positive input.
PIC18F97J94 FAMILY EXAMPLE 22-5: SCANNING AND CONVERTING ALL 16 CHANNELS PER SINGLE INTERRUPT A/D Configuration: • • • • • • • Select Any Channel for S/H+ Input (CH0SA<4:0> = xxxxx) Select VR- for S/H- Input (CH0NA<2:0> = 000) Use Only MUX A for Sampling (ALTS = 0) Configure MUX A for Input Scan (CSCNA = 1) Include All Analog Channels in Scanning (AD1CSSL = 1111 1111 1111 1111) Set AD1IF on Every 16th Sample (SMPI<4:0> = 01111) Configure Buffers for Single, 16-Word Results (BUFM = 0) Operational Sequenc
PIC18F97J94 FAMILY 22.8.3 USING DUAL BUFFERS Figure 22-18 and Example 22-6 demonstrate using dual buffers and alternating the buffer fill. Setting the BUFM bit enables dual buffers. In this example, an interrupt is generated after each sample. The BUFM setting does not affect other operational parameters. First, the conversion sequence starts filling the buffer at ADCBUF0. After the first interrupt occurs, the buffer begins to fill at ADCBUF8. The BUFS status bit is toggled after each interrupt.
PIC18F97J94 FAMILY EXAMPLE 22-6: CONVERTING A SINGLE CHANNEL, ONCE PER INTERRUPT, DUAL BUFFER MODE A/D Configuration: • • • • • • Select AN3 for S/H+ Input (CH0SA<4:0> = 00011) Select VR- for S/H- Input (CH0NA<2:0> = 000) Configure for No Input Scan (CSCNA = 0) Use Only MUX A for Sampling (ALTS = 0) Set AD1IF on Every Sample (SMPI<4:0> = 00000) Configure Buffer as Dual, 8-Word Segments (BUFM = 1) Operational Sequence: 1. 2. 3. 4. 5. Sample MUX A Input, AN3; Convert and Write to Buffer 0h.
PIC18F97J94 FAMILY FIGURE 22-19: Conversion Trigger CONVERTING TWO INPUTS USING ALTERNATING INPUT SELECTIONS TSAMP TSAMP TSAMP TSAMP TSAMP A/D CLK TCONVTCONV Analog Input AN1 TCONVTCONV AN15 TCONVTCONV AN15 TCONVTCONV AN1 TCONVTCONV AN15 ASAM SAMP Cleared in Software DONE BUFS ADC1BUF0 ADC1BUF1 ADC1BUF2 ADC1BUF3 ADC1BUF4 ADC1BUF5 ADC1BUF6 ADC1BUF7 ADC1BUF8 ADC1BUF9 ADC1BUFA ADC1BUFB AD1IF Cleared by Software 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY EXAMPLE 22-7: CONVERTING TWO INPUTS BY ALTERNATING MUX A AND MUX B A/D Configuration: • • • • • • • • Select AN1 for MUX A S/H+ Input (CH0SA<4:0> = 00001) Select VR- for MUX A S/H- Input (CH0NA<2:0> = 000) Configure for No Input Scan (CSCNA = 0) Select AN15 for MUX B S/H+ Input (CH0SB<4:0> = 11111) Select VR- for MUX B S/H- Input (CH0NB<2:0> = 000) Alternate MUX A and MUX B for Sampling (ALTS = 1) Set AD1IF on Every 8th Sample (SMPI<4:0> = 00111) Configure Buffer as Two, 8-Word Segment
PIC18F97J94 FAMILY 22.9 A/D Sampling Requirements The Analog Input model of the 12-bit A/D Converter is shown in Figure 22-20. The total sampling time for the A/D is a function of the holding capacitor charge time. For the A/D Converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the voltage level on the analog input pin.
PIC18F97J94 FAMILY FIGURE 22-21: 12-BIT A/D TRANSFER FUNCTION Output Code (Binary (Decimal)) 1111 1111 1111 (4095) 1111 1111 1110 (4094) 0010 0000 0011 (2051) 0010 0000 0010 (2050) 0010 0000 0001 (2049) 0010 0000 0000 (2048) 0001 1111 1111 (2047) 0001 1111 1110 (2046) 0001 1111 1101 (2045) 0000 0000 0001 (1) (VINH – VINL) VR+ 4096 4095 * (VR + – VR-) VR- + 4096 VR- + 2048 * (VR+ – VR-) 4096 VR- + Voltage Level VR+ – VR- 0 VR- 0000 0000 0000 (0) For the 10-bit transfer function (when 10-bi
PIC18F97J94 FAMILY FIGURE 22-22: 10-BIT A/D TRANSFER FUNCTION Output Code (Binary (Decimal)) 11 1111 1111 (1023) 11 1111 1110 (1022) 10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 (510) 01 1111 1101 (509) 00 0000 0001 (1) (VINH – VINL) VR+ 1024 1023 * (VR+ – VR-) VR- + 1024 VR- + 512 * (VR+ – VR-) 1024 VR- + Voltage Level VR+ – VR- 0 VR- 00 0000 0000 (0) 22.11 Operation During Sleep and Idle Modes 22.11.
PIC18F97J94 FAMILY To minimize the effects of digital noise on the A/D module operation, the user should select a conversion trigger source that ensures the A/D conversion will take place in Sleep mode. The automatic conversion trigger option can be used for sampling and conversion in Sleep (SSRC<3:0> = 0111). To use the automatic conversion option, the ADON bit should be set in the instruction prior to the SLEEP instruction.
PIC18F97J94 FAMILY 23.0 COMPARATOR MODULE 23.1 The analog comparator module contains three comparators that can be independently configured in a variety of ways. The inputs can be selected from the analog inputs and two internal voltage references. The digital outputs are available at the pin level, via PPS-Lite, and can also be read through the control register. Multiple output and interrupt event generations are also available. A generic single comparator from the module is shown in Figure 23-1.
PIC18F97J94 FAMILY REGISTER 23-1: CMxCON: COMPARATOR CONTROL x REGISTER R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 6 COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin
PIC18F97J94 FAMILY REGISTER 23-2: CMSTAT: COMPARATOR STATUS REGISTER U-0 U-0 U-0 U-0 U-0 R-x R-x R-x — — — — — C3OUT C2OUT C1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 C3OUT:C1OUT: Comparator x Status bits If CPOL (CMxCON<5>)= 0 (non-inverted polarity): 1 = Comparator x’s VIN+ > VIN0 = Comparator x’s VIN+ < VINCPOL = 1 (inverted pol
PIC18F97J94 FAMILY 23.2 Comparator Operation 23.3 Comparator Response Time A single comparator is shown in Figure 23-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input, VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input, VIN-, the output of the comparator is a digital high level.
PIC18F97J94 FAMILY 23.5 Comparator Control and Configuration 23.5.1 Each comparator has up to eight possible combinations of inputs: up to four external analog inputs and one of two internal voltage references. All of the comparators allow a selection of the signal from pin, CxINA, or the voltage from the Comparator Reference (CVREF) on the non-inverting channel. This is compared to either CxINB, CxINC, C2IND or the microcontroller’s fixed internal reference voltage (VBG, 1.
PIC18F97J94 FAMILY The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications, as discussed in Section 23.2 “Comparator Operation”. By default, the comparator’s output is at logic high whenever the voltage on VIN+ is greater than on VIN-. The polarity of the comparator outputs can be inverted using the CPOL bit (CMxCON<5>).
PIC18F97J94 FAMILY 23.6 Comparator Interrupts The comparator interrupt flag is set whenever any of the following occurs: • Low-to-high transition of the comparator output • High-to-low transition of the comparator output • Any change in the comparator output The comparator interrupt selection is done by the EVPOL<1:0> bits in the CMxCON register (CMxCON<4:3>). In order to provide maximum flexibility, the output of the comparator may be inverted using the CPOL bit in the CMxCON register (CMxCON<5>).
PIC18F97J94 FAMILY 23.7 Comparator Operation During Sleep When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional, if enabled. This interrupt will wake-up the device from Sleep mode when enabled. Each operational comparator will consume additional current. 23.8 Effects of a Reset A device Reset forces the CMxCON registers to their Reset state. This forces both comparators and the voltage reference to the OFF state.
PIC18F97J94 FAMILY 24.0 COMPARATOR VOLTAGE REFERENCE MODULE EQUATION 24-1: If CVRSS = 1: The comparator voltage reference is a 32-tap resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. A block diagram of the module is shown in Figure 24-1.
PIC18F97J94 FAMILY REGISTER 24-2: CVRCONL: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER LOW R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 CVREN CVROE CVRPSS1 CVRPSS0 — — — CVRNSS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit is powered on 0 = CVREF circuit is powered down bit 6 CVROE: Comparator
PIC18F97J94 FAMILY 24.2 Voltage Reference Accuracy/Error The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 24-1) keep CVREF from approaching the reference source rails. The voltage reference is derived from the reference source; therefore, the CVREF output changes with fluctuations in that source. The tested absolute accuracy of the voltage reference can be found in Section 31.
PIC18F97J94 FAMILY NOTES: DS30575A-page 500 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 25.0 HIGH/LOW-VOLTAGE DETECT (HLVD) The PIC18F97J94 family of devices has a High/LowVoltage Detect module (HLVD). This is a programmable circuit that sets both a device voltage trip point and the direction of change from that point. If the device experiences an excursion past the trip point in that direction, an interrupt flag is set. If the interrupt is enabled, the program execution branches to the interrupt vector address and the software responds to the interrupt.
PIC18F97J94 FAMILY The module is enabled by setting the HLVDEN bit (HLVDCON<4>). Each time the HLVD module is enabled, the circuitry requires some time to stabilize. The IRVST bit (HLVDCON<5>) is a read-only bit used to indicate when the circuit is stable. The module can only generate an interrupt after the circuit is stable and IRVST is set. trip point voltage.
PIC18F97J94 FAMILY 25.2 HLVD Setup To set up the HLVD module: 1. 2. 3. 4. 5. Select the desired HLVD trip point by writing the value to the HLVDL<3:0> bits. Set the VDIRMAG bit to detect high voltage (VDIRMAG = 1) or low voltage (VDIRMAG = 0). Enable the HLVD module by setting the HLVDEN bit. Clear the HLVD interrupt flag (PIR2<2>), which may have been set from a previous interrupt.
PIC18F97J94 FAMILY FIGURE 25-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0) CASE 1: HLVDIF will Not be Set VDD VHLVD HLVDIF Enable HLVD TIRVST IRVST HLVDIF Cleared in Software Internal Reference is Stable CASE 2: VDD VHLVD HLVDIF Enable HLVD TIRVST IRVST HLVDIF Cleared in Software Internal Reference is Stable HLVDIF Cleared in Software, HLVDIF Remains Set Since HLVD Condition still Exists HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) FIGURE 25-3: CASE 1: HLVDIF will not be Set VHLVD VDD HLVDIF
PIC18F97J94 FAMILY 25.5 Applications 25.6 In many applications, it is desirable to detect a drop below, or rise above, a particular voltage threshold. For example, the HLVD module could be periodically enabled to detect Universal Serial Bus (USB) attach or detach. This assumes the device is powered by a lower voltage source than the USB when detached. An attach would indicate a high-voltage detect from, for example, 3.3V to 5V (the voltage on USB) and vice versa for a detach.
PIC18F97J94 FAMILY NOTES: DS30575A-page 506 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 26.
PIC18F97J94 FAMILY 26.1 CTMU Registers The CTMUCON1 and CTMUCON3 registers (Register 26-1 and Register 26-3) contain control bits for configuring the CTMU module edge source selection, edge source polarity selection, edge sequencing, A/D trigger, analog circuit capacitor discharge and enables. The CTMUCON2 register (Register 26-2) has bits for selecting the current source range and current source trim.
PIC18F97J94 FAMILY REGISTER 26-2: CTMUCON2: CTMU CURRENT CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change (+62% typ.) from nominal current 011110 . . .
PIC18F97J94 FAMILY REGISTER 26-3: R/W-0 EDG2EN CTMUCON3: CTMU CURRENT CONTROL REGISTER 3 R/W-0 EDG2POL R/W-0 EDG2SEL3 R/W-0 EDG2SEL2 R/W-0 EDG2SEL1 R/W-0 U-0 U-0 EDG2SEL0 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 EDG2EN: Edge 2 Edge-Sensitive Select bit 1 = Input is edge-sensitive 0 = Input is level-sensitive bit 6 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 is programme
PIC18F97J94 FAMILY REGISTER 26-4: CTMUCON4: CTMU CURRENT CONTROL REGISTER 4 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 EDG1EN EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 EDG1EN: Edge 1 Edge-Sensitive Select bit 1 = Input is edge-sensitive 0 = Input is level-sensitive bit 6 EDG1POL: Edge 1 Polarity Select bit 1 =
PIC18F97J94 FAMILY 26.2 CTMU Operation The CTMU works by using a fixed current source to charge a circuit. The type of circuit depends on the type of measurement being made. In the case of charge measurement, the current is fixed and the amount of time the current is applied to the circuit is fixed. The amount of voltage read by the A/D becomes a measurement of the circuit’s capacitance. In the case of time measurement, the current, as well as the capacitance of the circuit, is fixed.
PIC18F97J94 FAMILY 26.2.5 INTERRUPTS The CTMU sets its interrupt flag (PIR3<3>) whenever the current source is enabled, then disabled. An interrupt is generated only if the corresponding interrupt enable bit (PIE3<3>) is also set. If edge sequencing is not enabled (i.e., Edge 1 must occur before Edge 2), it is necessary to monitor the Edge Status bits, and determine which edge occurred last and caused the interrupt. 26.
PIC18F97J94 FAMILY The CTMU current source may be trimmed with the ITRIMx bits in CTMUCON1, using an iterative process to get the exact current desired. Alternatively, the nominal value without adjustment may be used. That value may be stored by software for use in all subsequent capacitive or time measurements. To calculate the optimal value for RCAL, the nominal current must be chosen. For example, if the A/D Converter reference voltage is 3.3V, use 70% of full scale (or 2.
PIC18F97J94 FAMILY EXAMPLE 26-1: SETUP FOR CTMU CALIBRATION ROUTINES #include "p18cxxx.
PIC18F97J94 FAMILY EXAMPLE 26-2: CTMU CURRENT CALIBRATION ROUTINE #include "p18cxxx.h" #define COUNT 500 #define DELAY for(i=0;i
PIC18F97J94 FAMILY 26.4.2 CAPACITANCE CALIBRATION There is a small amount of capacitance from the internal A/D Converter sample capacitor, as well as stray capacitance from the circuit board traces and pads that affect the precision of capacitance measurements. A measurement of the stray capacitance can be taken by making sure the desired capacitance to be measured has been removed. After removing the capacitance to be measured: 1. 2. 3. 4. 5. 6. Initialize the A/D Converter and the CTMU.
PIC18F97J94 FAMILY EXAMPLE 26-3: CTMU CAPACITANCE CALIBRATION ROUTINE #include "p18cxxx.h" #define #define #define #define #define #define COUNT 25 ETIME COUNT*2.5 DELAY for(i=0;i
PIC18F97J94 FAMILY 26.5 Measuring Capacitance with the CTMU There are two ways to measure capacitance with the CTMU. The absolute method measures the actual capacitance value. The relative method only measures for any change in the capacitance. 26.5.1 ABSOLUTE CAPACITANCE MEASUREMENT For absolute capacitance measurements, both the current and capacitance calibration steps found in Section 26.4 “Calibrating the CTMU Module” should be followed. To perform these measurements: 1. 2. 3. 4. 5. 6. 7. 8.
PIC18F97J94 FAMILY EXAMPLE 26-4: CTMU ROUTINE FOR CAPACITIVE TOUCH SWITCH #include "p18cxxx.h" #define #define #define #define COUNT 500 DELAY for(i=0;i
PIC18F97J94 FAMILY 26.6 Measuring Time with the CTMU Module Time can be precisely measured after the ratio (C/I) is measured from the current and capacitance calibration step. To do that: 1. 2. 3. 4. 5. Initialize the A/D Converter and the CTMU. Set EDG1STAT. Set EDG2STAT. Perform an A/D conversion. Calculate the time between edges as T = (C/I) * V, where: • I is calculated in the current calibration step (Section 26.4.
PIC18F97J94 FAMILY 26.7 Measuring Temperature with the CTMU The constant-current source provided by the CTMU module can be used for low-cost temperature measurement by exploiting a basic property of common and inexpensive diodes. An on-chip temperature sense diode is provided on A/D Channel 29 to further simplify design and cost. 26.7.
PIC18F97J94 FAMILY 26.8 26.8.1 Operation During Sleep/Idle Modes SLEEP MODE When the device enters any Sleep mode, the CTMU module current source is always disabled. If the CTMU is performing an operation that depends on the current source when Sleep mode is invoked, the operation may not terminate correctly. Capacitance and time measurements may return erroneous values. 26.8.2 IDLE MODE The behavior of the CTMU in Idle mode is determined by the CTMUSIDL bit (CTMUCON<5>).
PIC18F97J94 FAMILY NOTES: DS30575A-page 524 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 27.0 UNIVERSAL SERIAL BUS (USB) 27.1 PIC18F97J94 family devices contain a full-speed and low-speed, compatible USB Serial Interface Engine (SIE) that allows fast communication between any USB host and the PIC® MCU. The SIE can be interfaced directly to the USB, utilizing the internal transceiver. This section describes the details of the USB peripheral. Because of the very specific nature of the module, some knowledge of USB is expected.
PIC18F97J94 FAMILY 27.2 USB Status and Control The operation of the USB module is configured and managed through three control registers. In addition, a total of 22 registers are used to manage the actual USB transactions. The registers are: • • • • • • USB Control Register (UCON) USB Configuration Register (UCFG) USB Transfer Status Register (USTAT) USB Device Address Register (UADDR) Frame Number Registers (UFRMH:UFRML) Endpoint Enable Registers 0 through 15 (UEPn) 27.2.
PIC18F97J94 FAMILY REGISTER 27-1: UCON: USB CONTROL REGISTER U-0 R/W-0 R-x R/C-0 R/W-0 R/W-0 R/W-0 U-0 — PPBRST(2) SE0 PKTDIS USBEN(1) RESUME SUSPND — bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 PPBRST: Ping-Pong Buffers Reset bit(2) 1 = Reset all Ping-Pong Buffer Pointers to the Even Buffer Descriptor
PIC18F97J94 FAMILY The PPBRST bit (UCON<6>) controls the Reset status when Double-Buffering mode (ping-pong buffering) is used. When the PPBRST bit is set, all Ping-Pong Buffer Pointers are set to the Even buffers. PPBRST has to be cleared by firmware. This bit is ignored in buffering modes not using ping-pong buffering. The PKTDIS bit (UCON<4>) is a flag indicating that the SIE has disabled packet transmission and reception.
PIC18F97J94 FAMILY REGISTER 27-2: R/W-0 UCFG: USB CONFIGURATION REGISTER R/W-0 UTEYE UOEMON U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — UPUEN(1,2) UTRDIS(1,3) FSEN(1) PPB1 PPB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UTEYE: USB Eye Pattern Test Enable bit 1 = Eye pattern test is enabled 0 = Eye pattern test is disabled bit 6 UOEMON: USB OE Monitor Enable bit 1
PIC18F97J94 FAMILY 27.2.2.2 Internal Pull-up Resistors The PIC18F97J94 family devices have built-in pull-up resistors, designed to meet the requirements for lowspeed and full-speed USB. The UPUEN bit (UCFG<4>) enables the internal pull-ups. Figure 27-1 shows the pull-ups and their control. Note: 27.2.2.3 A compliant USB device should never source any current onto the +5V VBUS line of the USB cable.
PIC18F97J94 FAMILY 27.2.3 USB STATUS REGISTER (USTAT) The USB Status register reports the transaction status within the SIE. When the SIE issues a USB transfer complete interrupt, USTAT should be read to determine the status of the transfer. USTAT contains the transfer endpoint number, direction and Ping-Pong Buffer Pointer value (if used). Note: The data in the USB Status register is valid only when the TRNIF interrupt flag is asserted.
PIC18F97J94 FAMILY 27.2.4 USB ENDPOINT CONTROL Each of the 16 possible bidirectional endpoints has its own independent control register, UEPn (where ‘n’ represents the endpoint number). Each register has an identical complement of control bits. Register 27-4 provides the prototype. The EPHSHK bit (UEPn<4>) controls handshaking for the endpoint; setting this bit enables USB handshaking. Typically, this bit is always set except when using isochronous endpoints.
PIC18F97J94 FAMILY 27.2.5 USB ADDRESS REGISTER (UADDR) FIGURE 27-4: The USB Address register contains the unique USB address that the peripheral will decode when active. UADDR is reset to 00h when a USB Reset is received, indicated by URSTIF, or when a Reset is received from the microcontroller. The USB address must be written by the microcontroller during the USB setup phase (enumeration) as part of the Microchip USB firmware support. 27.2.
PIC18F97J94 FAMILY 27.4 Buffer Descriptors and the Buffer Descriptor Table The registers in Bank 13 are used specifically for endpoint buffer control in a structure known as the Buffer Descriptor Table (BDT). This provides a flexible method for users to construct and control endpoint buffers of various lengths and configuration. The BDT is composed of Buffer Descriptors (BD) which are used to define and control the actual buffers in the USB RAM space.
PIC18F97J94 FAMILY The BDnSTAT byte of the BDT should always be the last byte updated when preparing to arm an endpoint. The SIE will clear the UOWN bit when a transaction has completed. No hardware mechanism exists to block access when the UOWN bit is set. Thus, unexpected behavior can occur if the microcontroller attempts to modify memory when the SIE owns it. Similarly, reading such memory may produce inaccurate data until the USB peripheral returns ownership to the microcontroller. 27.4.1.
PIC18F97J94 FAMILY REGISTER 27-5: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH BD63STAT), CPU MODE R/W-x R/W-x U-0 U-0 R/W-x R/W-x R/W-x R/W-x UOWN(1) DTS(2) —(3) —(3) DTSEN BSTALL BC9 BC8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UOWN: USB Own bit(1) 0 = The microcontroller core owns the BD and its corresponding buffer bit 6 DTS: Data
PIC18F97J94 FAMILY 27.4.1.3 BDnSTAT Register (SIE Mode) When the BD and its buffer are owned by the SIE, most of the bits in BDnSTAT take on a different meaning. The configuration is shown in Register 27-6. Once UOWN is set, any data or control settings previously written there by the user will be overwritten with data from the SIE. The BDnSTAT register is updated by the SIE with the token Packet Identifier (PID) which is stored in BDnSTAT<5:2>.
PIC18F97J94 FAMILY 27.4.4 PING-PONG BUFFERING the completion of a transaction (UOWN cleared by the SIE), the pointer is toggled to the Odd BD. After the completion of the next transaction, the pointer is toggled back to the Even BD and so on. An endpoint is defined to have a ping-pong buffer when it has two sets of BD entries: one set for an Even transfer and one set for an Odd transfer. This allows the CPU to process one BD while the SIE is processing the other BD.
PIC18F97J94 FAMILY TABLE 27-2: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT BUFFERING MODES BDs Assigned to Endpoint Mode 0 (No Ping-Pong) Endpoint Out Mode 1 (Ping-Pong on EP0 OUT) In Out Mode 3 (Ping-Pong on All Other EPs, except EP0) Mode 2 (Ping-Pong on All EPs) In Out In Out In 0 0 1 0 (E), 1 (O) 2 0 (E), 1 (O) 2 (E), 3 (O) 0 1 1 2 3 3 4 4 (E), 5 (O) 6 (E), 7 (O) 2 (E), 3 (O) 4 (E), 5 (O) 2 4 5 5 6 8 (E), 9 (O) 10 (E), 11 (O) 6 (E), 7 (O) 8 (E), 9 (O) 3
PIC18F97J94 FAMILY 27.5 USB Interrupts Figure 27-7 provides the interrupt logic for the USB module. There are two layers of interrupt registers in the USB module. The top level consists of overall USB status interrupts; these are enabled and flagged in the UIE and UIR registers, respectively. The second level consists of USB error conditions, which are enabled and flagged in the UEIR and UEIE registers. An interrupt condition in any of these triggers a USB Error Interrupt Flag (UERRIF) in the top level.
PIC18F97J94 FAMILY 27.5.1 USB INTERRUPT STATUS REGISTER (UIR) When the USB module is in the Low-Power Suspend mode (UCON<1> = 1), the SIE does not get clocked. When in this state, the SIE cannot process packets, and therefore, cannot detect new interrupt conditions other than the Activity Detect Interrupt, ACTVIF. The ACTVIF bit is typically used by USB firmware to detect when the microcontroller should bring the USB module out of the Low-Power Suspend mode (UCON<1> = 0).
PIC18F97J94 FAMILY 27.5.1.1 Bus Activity Detect Interrupt Bit (ACTVIF) The ACTVIF bit cannot be cleared immediately after the USB module wakes up from Suspend mode or while the USB module is suspended. A few clock cycles are required to synchronize the internal hardware state machine before the ACTVIF bit can be cleared by firmware. Clearing the ACTVIF bit before the internal hardware is synchronized may not have an effect on the value of ACTVIF.
PIC18F97J94 FAMILY 27.5.2 USB INTERRUPT ENABLE REGISTER (UIE) The USB Interrupt Enable (UIE) register (Register 27-8) contains the enable bits for the USB status interrupt sources. Setting any of these bits will enable the respective interrupt source in the UIR register. Register 27-8: The values in this register only affect the propagation of an interrupt condition to the microcontroller’s interrupt logic.
PIC18F97J94 FAMILY 27.5.3 USB ERROR INTERRUPT STATUS REGISTER (UEIR) The USB Error Interrupt Status register (Register 27-9) contains the flag bits for each of the error sources within the USB peripheral. Each of these sources is controlled by a corresponding interrupt enable bit in the UEIE register. All of the USB error flags are ORed together to generate the USB Error Interrupt Flag (UERRIF) at the top level of the interrupt logic.
PIC18F97J94 FAMILY 27.5.4 USB ERROR INTERRUPT ENABLE REGISTER (UEIE) As with the UIE register, the enable bits only affect the propagation of an interrupt condition to the microcontroller’s interrupt logic. The flag bits are still set by their interrupt conditions, allowing them to be polled and serviced without actually generating an interrupt. The USB Error Interrupt Enable register (Register 27-10) contains the enable bits for each of the USB error interrupt sources.
PIC18F97J94 FAMILY 27.6 USB Power Modes Many USB applications will likely have several different sets of power requirements and configuration. The most common power modes encountered are Bus Power Only, Self-Power Only and Dual Power with Self-Power Dominance. The most common cases are presented here. Also provided is a means of estimating the current consumption of the USB transceiver. 27.6.1 The application should never source any current onto the 5V VBUS pin of the USB cable.
PIC18F97J94 FAMILY 27.6.4 USB TRANSCEIVER CURRENT CONSUMPTION The USB transceiver consumes a variable amount of current depending on the characteristic impedance of the USB cable, the length of the cable, the VUSB3V3 supply voltage and the actual data patterns moving across the USB cable. Longer cables have larger capacitances and consume more total energy when switching output states. Data patterns that consist of “IN” traffic consume far more current than “OUT” traffic.
PIC18F97J94 FAMILY EQUATION 27-2: CALCULATING USB TRANSCEIVER CURRENT† For this example, the following assumptions are made about the application: • 3.3V will be applied to VUSB3V3 and VDD, with the core voltage regulator enabled. • This is a full-speed application that uses one interrupt IN endpoint that can send one packet of 64 bytes every 1 ms, with no restrictions on the values of the bytes being sent. The application may or may not have additional traffic on OUT endpoints.
PIC18F97J94 FAMILY 27.7 Oscillator 27.8 The USB module has specific clock requirements. For full-speed operation, the clock source must be 48 MHz. Even so, the microcontroller core and other peripherals are not required to run at that clock speed. TABLE 27-4: Name INTCON IPR2 USB Firmware and Drivers Microchip provides a number of application-specific resources, such as USB firmware and driver support. Refer to www.microchip.com for the latest firmware and driver support.
PIC18F97J94 FAMILY 27.9 Overview of USB 27.9.2 This section presents some of the basic USB concepts and useful information necessary to design a USB device. Although much information is provided in this section, there is a plethora of information provided within the USB specifications and class specifications. Thus, the reader is encouraged to refer to the USB specifications for more information (www.usb.org).
PIC18F97J94 FAMILY The USB Specification limits the power taken from the bus. Each device is ensured 100 mA at approximately 5V (one unit load). Additional power may be requested, up to a maximum of 500 mA. Note that power above one unit load is a request and the host or hub is not obligated to provide the extra current. Thus, a device capable of consuming more than one unit load must be able to maintain a low-power configuration of a one unit load or less, if necessary.
PIC18F97J94 FAMILY NOTES: DS30575A-page 552 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 28.0 SPECIAL FEATURES OF THE CPU The PIC18F97J94 family of devices includes several features intended to maximize reliability and minimize cost through elimination of external components.
PIC18F97J94 FAMILY TABLE 28-1: MAPPING OF THE FLASH CONFIGURATION WORDS TO THE CONFIGURATION REGISTERS Configuration Register (Volatile) Configuration Register Address Flash Configuration Byte Address CONFIG1L 300000h XXXF0h CONFIG1H 300001h XXXF1h CONFIG2L 300002h XXXF2h CONFIG2H 300003h XXXF3h CONFIG3L 300004h XXXF4h CONFIG3H 300005h XXXF5h CONFIG4L 300006h XXXF6h CONFIG4H 300007h XXXF7h CONFIG5L 300008h XXXF8h CONFIG5H 300009h XXXF9h CONFIG6L 30000Ah XXXFAh CONFIG6H
PIC18F97J94 FAMILY REGISTER 28-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h) R/WO-1 R/WO-1 R/WO-1 U-1 U-1 U-1 U-1 U-1 DEBUG XINST STVREN — — — — — bit 7 bit 0 Legend: P = Programmable bit WO = Write-Once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger is disabled, and RB6 and RB7 are configure
PIC18F97J94 FAMILY REGISTER 28-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)(1,2,3,4) R/WO-1 U-1 R/WO-0 U-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 IESO — CLKOEN — SOSCSEL FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: P = Programmable bit WO = Write-Once bit R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IESO: Internal External Switch Over bit 1 = Internal/External Switchover mode is enabl
PIC18F97J94 FAMILY CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)(1,2) REGISTER 28-4: U-1 U-1 U-1 U-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 — — — — PLLDIV3(3) PLLDIV2(3) PLLDIV1(3) PLLDIV0(3) bit 7 bit 0 Legend: P = Programmable bit WO = Write-Once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Program the corresponding Flash Configuration bit to ‘1’
PIC18F97J94 FAMILY REGISTER 28-5: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h)(1,2) U-1 U-1 R/WO-1 R/WO-1 U-1 U-0 R/WO-1 R/WO-1 — — FSCM1 FSCM0 — — POSCMD1 POSCMD0 bit 7 bit 0 Legend: P = Programmable bit WO = Write-Once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘1’ bit 5-4 FSCM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x
PIC18F97J94 FAMILY REGISTER 28-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 WPFP7 WPFP6 WPFP5 WPFP4 WPFP3 WPFP2 WPFP1 WPFP0 bit 7 bit 0 Legend: P = Programmable bit WO = Write-Once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown WPFP<7:0>: Write-Protect Program Flash Pages bits (valid when WPDIS
PIC18F97J94 FAMILY REGISTER 28-8: R/WO-1 WAIT (1) CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) R/WO-1 R/WO-1 R/WO-1 R/WO-1 U-1 R/WO-1 R/WO-1 BW ABW1 ABW0 EASHFT — CINASEL T5GSEL bit 7 bit 0 Legend: P = Programmable bit WO = Write-Once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WAIT: External Bus Wait Enable bit(1) 1 = Wait selections from WAIT<1:0> (ME
PIC18F97J94 FAMILY REGISTER 28-9: CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h) U-1 U-1 U-1 U-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 — — — — MSSPMSK1 MSSPMSK2 LS48MHZ IOL1WAY bit 7 bit 0 Legend: P = Programmable bit WO = Write-Once bit R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Program the corresponding Flash Configuration bit to ‘1’ bit 3 MSSPMSK1: MSSP1 7-
PIC18F97J94 FAMILY REGISTER 28-10: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 WDPS3 WDPS2 WDPS1 WDPS0 WDTCLK1 WDTCLK0 WDTWIN1 WDTWIN0 bit 7 bit 0 Legend: P = Programmable bit WO = Write-Once bit R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 WDPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:1
PIC18F97J94 FAMILY REGISTER 28-11: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh) U-1 U-1 U-1 U-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 — — — — WPSA WINDIS WDTEN1 WDTEN0 bit 7 bit 0 Legend: P = Programmable bit WO = Write-Once bit R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Program the corresponding Flash Configuration bit to ‘1’ bit 3 WPSA: WDT Prescaler bit 1 =
PIC18F97J94 FAMILY REGISTER 28-12: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) U-1 U-1 U-1 R/WO-1 R/WO-1 R/WO-1 U-1 R/WO-1 — — — DSBITEN DSBOREN VBTBOR — RETEN bit 7 bit 0 Legend: P = Programmable bit WO = Write-Once bit R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘1’ bit 4 DSBITEN: DSEN Bit Enable bit 1 = Deep Sleep is controlled by the regis
PIC18F97J94 FAMILY REGISTER 28-13: CONFIG8L: CONFIGURATION REGISTER 8 LOW (BYTE ADDRESS 30000Eh) R/WO-1 DSWDTPS4 R/WO-1 R/WO-1 R/WO-1 R/WO-1 DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0 U-1 U-1 U-1 — — — bit 7 bit 0 Legend: P = Programmable bit WO = Write-Once bit R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 DSWDTPS<4:0>: Deep Sleep Watchdog Timer Postscale Select bits The DS WDT prescaler is 32; th
PIC18F97J94 FAMILY REGISTER 28-14: CONFIG8H: CONFIGURATION REGISTER 8 HIGH (BYTE ADDRESS 30000Fh) U-1 U-1 U-1 U-1 U-1 U-1 R/WO-1 R/WO-1 — — — — — — DSWDTOSC DSWDTEN bit 7 bit 0 Legend: P = Programmable bit WO = Write-Once bit R = Readable bit W = Writable bit U = Unimplemented bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Program the corresponding Flash Configuration bit to ‘1’ bit 3-2 Unimplemented: Read as ‘1’ bit 1 D
PIC18F97J94 FAMILY REGISTER 28-15: DEVID2: DEVICE ID REGISTER 2 FOR THE PIC18F97J94 R R R R R R R R DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown DEV<10:3>: Device ID bits These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number.
PIC18F97J94 FAMILY 28.2 Watchdog Timer (WDT) Windowed WDT mode is enabled by programming the WINDIS Configuration bit (CONFIG6H<2>) to ‘0’. For the PIC18F97J94 family of devices, the WDT is driven by the LF-INTOSC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the LF-INTOSC Oscillator. The WDT can be operated in one of four modes, as determined by WDTEN<1:0> (CONFIG6H<1:0>.
PIC18F97J94 FAMILY 28.2.2 CONTROL REGISTER Register 28-17 shows the RCON2 register. This is a readable and writable register which contains a control bit that allows software to override the WDT Enable Configuration bit, but only if the Configuration bit has disabled the WDT.
PIC18F97J94 FAMILY 28.3 Two-Speed Start-up In all other power-managed modes, Two-Speed Start-up is not used. The device will be clocked by the currently selected clock source until the primary clock source becomes available. The setting of the IESO Configuration bit is ignored.
PIC18F97J94 FAMILY 28.4 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block. The FSCM function is enabled by clearing the FSCMx Configuration bits. When FSCM is enabled, the LF-INTOSC Oscillator runs at all times to monitor clocks to peripherals and provides a backup clock in the event of a clock failure.
PIC18F97J94 FAMILY FIGURE 28-4: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure Device Clock Output CM Output (Q) Failure Detected OSCFIF CM Test Note: 28.4.3 CM Test The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. FSCM INTERRUPTS IN POWER-MANAGED MODES By entering a power-managed mode, the clock multiplexer selects the clock source selected by the OSCCON register.
PIC18F97J94 FAMILY 28.4.5 PROGRAM VERIFICATION AND CODE PROTECTION For all devices in the PIC18F97J94 family of devices, the on-chip program memory space is treated as a single block. Code protection for this block is controlled by one Configuration bit, CP0. This bit inhibits external reads and writes to the program memory space. It has no direct effect in normal execution mode. 28.4.
PIC18F97J94 FAMILY NOTES: DS30575A-page 574 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 29.0 INSTRUCTION SET SUMMARY The PIC18F97J94 family of devices incorporates the standard set of 75 PIC18 core instructions, as well as an extended set of 8 new instructions for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 29.
PIC18F97J94 FAMILY TABLE 29-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
PIC18F97J94 FAMILY FIGURE 29-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 OPCODE Example Instruction 8 7 d 0 a ADDWF MYREG, W, B f (FILE #) d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE 15 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE
PIC18F97J94 FAMILY TABLE 29-2: PIC18F97J94 FAMILY INSTRUCTION SET Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d, a
PIC18F97J94 FAMILY TABLE 29-2: PIC18F97J94 FAMILY INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG f, b, a f, b, a f, b, a f, b, a f, b, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None
PIC18F97J94 FAMILY TABLE 29-2: PIC18F97J94 FAMILY INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add Literal and WREG AND Literal with WREG Inclusive OR Literal with WREG Move literal (12-bit) 2nd word to FSR(f) 1st word Move Literal to BSR<3:0> Move Literal to WREG Multiply Literal with WREG Return with Literal in WREG Sub
PIC18F97J94 FAMILY 29.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW Syntax: ADDWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) + (f) dest Status Affected: N, OV, C, DC, Z k Operands: 0 k 255 Operation: (W) + k W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
PIC18F97J94 FAMILY ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC Syntax: ANDLW Operands: 0 f 255 d [0,1] a [0,1] f {,d {,a}} Operation: (W) + (f) + (C) dest Status Affected: N,OV, C, DC, Z Encoding: 0010 Description: 00da ffff Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected.
PIC18F97J94 FAMILY ANDWF AND W with f BC Branch if Carry Syntax: ANDWF Syntax: BC Operands: 0 f 255 d [0,1] a [0,1] f {,d {,a}} Operation: (W) .AND. (f) dest Status Affected: N, Z Encoding: 0001 Description: Operands: -128 n 127 Operation: if Carry bit is ‘1’, (PC) + 2 + 2n PC Status Affected: None Encoding: 01da ffff ffff 1110 Description: The contents of W are ANDed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W.
PIC18F97J94 FAMILY BCF Bit Clear f BN Branch if Negative Syntax: BCF Syntax: BN Operands: 0 f 255 0b7 a [0,1] f, b {,a} Operation: 0 f Status Affected: None Encoding: 1001 Description: Operands: -128 n 127 Operation: if Negative bit is ‘1’, (PC) + 2 + 2n PC Status Affected: None Encoding: bbba ffff ffff 1110 Description: Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
PIC18F97J94 FAMILY BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC Syntax: BNN n n Operands: -128 n 127 Operands: -128 n 127 Operation: if Carry bit is ‘0’, (PC) + 2 + 2n PC Operation: if Negative bit is ‘0’, (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0011 nnnn nnnn If the Carry bit is ‘0’, then the program will branch. Encoding: 1110 Description: The 2’s complement number ‘2n’ is added to the PC.
PIC18F97J94 FAMILY BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV Syntax: BNZ n n Operands: -128 n 127 Operands: -128 n 127 Operation: if Overflow bit is ‘0’, (PC) + 2 + 2n PC Operation: if Zero bit is ‘0’, (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0101 nnnn nnnn If the Overflow bit is ‘0’, then the program will branch. Encoding: 1110 Description: The 2’s complement number ‘2n’ is added to the PC.
PIC18F97J94 FAMILY BRA Unconditional Branch BSF Bit Set f Syntax: BRA Syntax: BSF Operands: -1024 n 1023 Operands: Operation: (PC) + 2 + 2n PC Status Affected: None 0 f 255 0b7 a [0,1] Operation: 1 f Status Affected: None Encoding: n 1101 Description: 0nnn nnnn nnnn Add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction.
PIC18F97J94 FAMILY BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 f 255 0b7 a [0,1] Operands: 0 f 255 0b<7 a [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 1011 Description: bbba ffff ffff If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped.
PIC18F97J94 FAMILY BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV Operands: 0 f 255 0b<7 a [0,1] Operands: -128 n 127 Operation: if Overflow bit is ‘1’, (PC) + 2 + 2n PC Status Affected: None Operation: (f) f Status Affected: None Encoding: 0111 Description: Encoding: bbba ffff ffff 1110 Description: Bit ‘b’ in data memory location, ‘f’, is inverted.
PIC18F97J94 FAMILY BZ Branch if Zero CALL Subroutine Call Syntax: BZ Syntax: CALL k {,s} n Operands: -128 n 127 Operands: Operation: if Zero bit is ‘1’, (PC) + 2 + 2n PC 0 k 1048575 s [0,1] Operation: Status Affected: None (PC) + 4 TOS, k PC<20:1>; if s = 1 (W) WS, (STATUS) STATUSS, (BSR) BSRS Status Affected: None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is ‘1’, then the program will branch.
PIC18F97J94 FAMILY CLRF Clear f Syntax: CLRF Operands: 0 f 255 a [0,1] f {,a} Operation: 000h f, 1Z Status Affected: Z Encoding: 0110 Description: 101a ffff ffff Clears the contents of the specified register.
PIC18F97J94 FAMILY COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF Syntax: CPFSEQ Operands: 0 f 255 a [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: f dest Status Affected: N, Z Encoding: 0001 Description: 11da ffff ffff The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W.
PIC18F97J94 FAMILY CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT Syntax: CPFSLT Operands: 0 f 255 a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) –W), skip if (f) > (W) (unsigned comparison) Operation: (f) –W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: Description: 0110 f {,a} 010a ffff ffff Compares the contents of data memory location ‘f’ to the contents of the W by
PIC18F97J94 FAMILY DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: Operation: If [W<3:0> > 9] or [DC = 1], then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0> 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest Status Affected: C, DC, N, OV, Z Encoding: If [W<7:4> > 9] or [C = 1], then (W<7:4>) + 6 W<7:4>; C =1; else (W<7:4>) W<7:4> Status Affected: 0000 Description: 0000 0000 0000 0111 Description: DAW adjusts
PIC18F97J94 FAMILY DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if Not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest, skip if result = 0 Operation: (f) – 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0010 Description: 11da ffff ffff The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W.
PIC18F97J94 FAMILY GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF Operands: 0 k 1048575 Operands: Operation: k PC<20:1> Status Affected: None 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 Description: GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range.
PIC18F97J94 FAMILY INCFSZ Increment f, Skip if 0 INFSNZ Syntax: INCFSZ Syntax: INFSNZ 0 f 255 d [0,1] a [0,1] f {,d {,a}} Increment f, Skip if Not 0 f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: Operation: (f) + 1 dest, skip if result = 0 Operation: (f) + 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0011 Description: 11da ffff ffff The contents of register ‘f’ are incremented.
PIC18F97J94 FAMILY IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF Operands: 0 k 255 Operands: Operation: (W) .OR. k W Status Affected: N, Z 0 f 255 d [0,1] a [0,1] Operation: (W) .OR. (f) dest Status Affected: N, Z Encoding: 0000 1001 kkkk kkkk Description: The contents of W are ORed with the eight-bit literal ‘k’. The result is placed in W.
PIC18F97J94 FAMILY LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF Operands: 0f2 0 k 4095 Operands: Operation: k FSRf 0 f 255 d [0,1] a [0,1] Status Affected: None Operation: f dest Status Affected: N, Z Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the file select register pointed to by ‘f’.
PIC18F97J94 FAMILY MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF fs,fd Syntax: MOVLB k Operands: 0 fs 4095 0 fd 4095 Operands: 0 k 255 Operation: k BSR Status Affected: None Operation: (fs) fd Status Affected: None Encoding: 1st word (source) 2nd word (destin.) Encoding: 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register, ‘fs’, are moved to destination register ‘fd’.
PIC18F97J94 FAMILY MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF Operands: 0 k 255 Operands: Operation: kW 0 f 255 a [0,1] Status Affected: None Encoding: 0000 Description: 1110 kkkk kkkk The eight-bit literal ‘k’ is loaded into W.
PIC18F97J94 FAMILY MULLW Multiply Literal with W MULWF Multiply W with f Syntax: MULLW Syntax: MULWF Operands: 0 f 255 a [0,1] Operation: (W) x (f) PRODH:PRODL Status Affected: None k Operands: 0 k 255 Operation: (W) x k PRODH:PRODL Status Affected: None Encoding: 0000 Description: 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in the PRODH:PRODL register pair.
PIC18F97J94 FAMILY NEGF Negate f Syntax: NEGF Operands: 0 f 255 a [0,1] f {,a} Operation: (f) + 1 f Status Affected: N, OV, C, DC, Z Encoding: 0110 Description: 110a ffff If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 29.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.
PIC18F97J94 FAMILY POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) bit bucket Operation: (PC + 2) TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
PIC18F97J94 FAMILY RCALL Relative Call RESET Reset Syntax: RCALL Syntax: RESET n Operands: -1024 n 1023 Operands: None Operation: (PC) + 2 TOS, (PC) + 2 + 2n PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 Description: 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack.
PIC18F97J94 FAMILY RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s [0,1] Operands: 0 k 255 Operation: (TOS) PC, 1 GIE/GIEH or PEIE/GIEL; if s = 1, (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged Operation: k W, (TOS) PC, PCLATU, PCLATH are unchanged Status Affected: None Status Affected: 0000 0000 Description: 0000 0001 Words: 1 Cycles: 2 Q Cycle Activity: kkkk kkkk W is loaded with th
PIC18F97J94 FAMILY RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF Operands: s [0,1] Operands: Operation: (TOS) PC; if s = 1, (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) C, (C) dest<0> Status Affected: C, N, Z Status Affected: None Encoding: 0000 Description: Encoding: 0000 0001 001s 0011 Description: Return from subroutine.
PIC18F97J94 FAMILY RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: RLNCF Syntax: RRCF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) dest<0> Operation: Status Affected: N, Z (f) dest, (f<0>) C, (C) dest<7> Status Affected: C, N, Z Encoding: 0100 Description: f {,d {,a}} 01da ffff ffff The contents of register ‘f’ are rotated one bit to the left.
PIC18F97J94 FAMILY RRNCF Rotate Right f (No Carry) SETF Set f Syntax: RRNCF Syntax: SETF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) dest, (f<0>) dest<7> Status Affected: N, Z Encoding: 0100 Description: f {,d {,a}} 00da Operation: FFh f Status Affected: None Encoding: ffff ffff 0110 Description: The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W.
PIC18F97J94 FAMILY SLEEP Enter Sleep Mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB Operands: None Operands: Operation: 00h WDT, 0 WDT postscaler, 1 TO, 0 PD 0 f 255 d [0,1] a [0,1] Operation: (W) – (f) – (C) dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Encoding: 0000 0000 0011 0101 Description: The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set.
PIC18F97J94 FAMILY SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF Operands: 0 k 255 Operands: Operation: k – (W) W Status Affected: N, OV, C, DC, Z 0 f 255 d [0,1] a [0,1] Operation: (f) – (W) dest Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk Description: W is subtracted from the eight-bit literal ‘k’. The result is placed in W.
PIC18F97J94 FAMILY SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB Syntax: SWAPF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – (W) – (C) dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> Status Affected: None Encoding: 0101 Description: f {,d {,a}} 10da ffff ffff Subtract W and the Carry flag (borrow) from register ‘f’ (2’s complement method).
PIC18F97J94 FAMILY TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) TABLAT; TBLPTR – No Change if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) + 1 TBLPTR if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) – 1 TBLPTR if TBLRD +*, (TBLPTR) + 1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT Status Affected: None Encoding: Description: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *=3 +* Before Inst
PIC18F97J94 FAMILY TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Operation: if TBLWT*, (TABLAT) Holding Register; TBLPTR – No Change if TBLWT*+, (TABLAT) Holding Register; (TBLPTR) + 1 TBLPTR if TBLWT*-, (TABLAT) Holding Register; (TBLPTR) – 1 TBLPTR if TBLWT+*, (TBLPTR) + 1 TBLPTR; (TABLAT) Holding Register Status Affected: Example 2: None Encoding: Description: Before Instruction TABLAT = 55h TBLPTR = 00A35
PIC18F97J94 FAMILY TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 f 255 a [0,1] Operands: 0 k 255 Operation: (W) .XOR. k W Status Affected: N, Z Operation: skip if f = 0 Status Affected: None Encoding: Encoding: 0110 Description: 011a ffff ffff If ‘f’ = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction.
PIC18F97J94 FAMILY XORWF Exclusive OR W with f Syntax: XORWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 Description: f {,d {,a}} 10da ffff ffff Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
PIC18F97J94 FAMILY 29.2 Extended Instruction Set A summary of the instructions in the extended instruction set is provided in Table 29-3. Detailed descriptions are provided in Section 29.2.2 “Extended Instruction Set”. The opcode field descriptions in Table 29-1 (page 576) apply to both the standard and extended PIC18 instruction sets.
PIC18F97J94 FAMILY 29.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 k 63 f [ 0, 1, 2 ] Operands: 0 k 63 Operation: Operation: FSR(f) + k FSR(f) FSR2 + k FSR2, (TOS) PC Status Affected: None Status Affected: None Encoding: 1110 1000 ffkk kkkk Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’.
PIC18F97J94 FAMILY CALLW Subroutine Call Using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [zs], fd Operands: None Operands: Operation: (PC + 2) TOS, (W) PCL, (PCLATH) PCH, (PCLATU) PCU 0 zs 127 0 fd 4095 Operation: ((FSR2) + zs) fd Status Affected: None Status Affected: None Encoding: 0000 Description 0000 0001 0100 First, the return address (PC + 2) is pushed onto the return stack.
PIC18F97J94 FAMILY MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0 zs 127 0 zd 127 Operands: 0k 255 Operation: k (FSR2), FSR2 – 1 FSR2 Status Affected: None Operation: ((FSR2) + zs) ((FSR2) + zd) Status Affected: None Encoding: 1st word (source) 2nd word (dest.
PIC18F97J94 FAMILY SUBFSR Subtract Literal from FSR SUBULNK Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 k 63 Operands: 0 k 63 f [ 0, 1, 2 ] Operation: Operation: FSRf – k FSRf FSR2 – k FSR2, (TOS) PC Status Affected: None Status Affected: None Encoding: 1110 1001 ffkk kkkk Description: The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘f’.
PIC18F97J94 FAMILY 29.2.3 Note: BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing (Section 6.6.1 “Indexed Addressing with Literal Offset”).
PIC18F97J94 FAMILY ADD W to Indexed (Indexed Literal Offset mode) BSF Bit Set Indexed (Indexed Literal Offset mode) Syntax: ADDWF Syntax: BSF [k], b Operands: 0 k 95 d [0,1] Operands: 0 f 95 0b7 Operation: (W) + ((FSR2) + k) dest Operation: 1 ((FSR2) + k) Status Affected: N, OV, C, DC, Z Status Affected: None ADDWF Encoding: [k] {,d} 0010 Description: 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offset by the valu
PIC18F97J94 FAMILY 29.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB® IDE TOOLS The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set for the PIC18F97J94 Family. This includes the MPLAB C18 C Compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device.
PIC18F97J94 FAMILY 30.
PIC18F97J94 FAMILY 30.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 30.
PIC18F97J94 FAMILY 30.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC18F97J94 FAMILY 30.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 30.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC18F97J94 FAMILY 31.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +100°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on MCLR with respect to VSS..............................................................................
PIC18F97J94 FAMILY FIGURE 31-1: VOLTAGE-FREQUENCY GRAPH, REGULATOR DISABLED (INDUSTRIAL)(1,2) 4V 3.75V 3.6V Voltage (VDD) 3.25V PIC18F97J94 Family 2V 4 MHz Note 1: 2: 3V 2.5V Frequency 64 MHz When the USB module is enabled, VUSB3V3 and VDD should be connected together and provided 3.0V-3.6V. When the USB module is not enabled, VUSB3V3 and VDD should still be connected together. VCAP (nominal on-chip regulator output voltage) = 1.8V. DS30575A-page 630 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 31.1 DC Characteristics: Supply Voltage PIC18F97J94 (Industrial) PIC18F97J94 (Industrial) Param Symbol No. D001 VDD Standard Operating Conditions: 2V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C Characteristic Supply Voltage Min Typ Max Units 2.0 — 3.6 V D001C AVDD Analog Supply Voltage VDD – 0.3 — VDD + 0.3 V D001D AVSS Analog Ground Potential VSS – 0.3 — VSS + 0.3 V D001E VUSB3V3 USB Supply Voltage 3 3.3 3.
PIC18F97J94 FAMILY 31.2 DC Characteristics: Power-Down and Supply Current PIC18F97J94 (Industrial) PIC18F97J94 Family (Industrial) Param No. Typ(1) Max Units 3.7 7.0 µA -40°C 3.7 7.0 µA +25°C 5.0 9.0 µA +60°C 9.0 18 µA +85°C 3.7 8.0 µA -40°C DC60 DC61 DC70 Note 1: 2: 3: 4: Conditions 3.7 8.0 µA +25°C 5.0 11.0 µA +60°C 10 20 µA +85°C 0.07 0.55 µA -40°C 0.09 0.55 µA +25°C 2.0 3.2 µA +60°C 7.0 8.5 µA +85°C 0.10 0.65 µA -40°C 0.15 0.
PIC18F97J94 FAMILY TABLE 31-2: Param No. DC CHARACTERISTICS: POWER-DOWN AND SUPPLY CURRENT PIC18F97J94 FAMILY (INDUSTRIAL) Device Typ Max Units Conditions Supply Current (IDD) All Devices TABLE 31-3: Param No. 22 55 µA -40°C to +85°C VDD = 2.0V 23 56 µA -40°C to +85°C VDD = 3.3V 21 54 µA -40°C to +85°C VDD =2.0V 22 55 µA -40°C to +85°C VDD = 3.
PIC18F97J94 FAMILY TABLE 31-4: Param No. DC CHARACTERISTICS: POWER-DOWN AND SUPPLY CURRENT PIC18F97J94 FAMILY (INDUSTRIAL) Device Typ Max Units Conditions 100 150 µA -40°C to +85°C VDD = 2.0V 105 155 µA -40°C to +85°C VDD = 3.3V 330 390 µA -40°C to +85°C VDD = 2.0V 340 405 µA -40°C to +85°C VDD = 3.3V 5.0 5.5 mA -40°C to +85°C VDD = 2.0V 5.0 5.5 mA -40°C to +85°C VDD = 3.3V 5.7 6.5 mA -40°C to +85°C VDD = 2.0V 5.7 7.0 mA -40°C to +85°C VDD = 3.
PIC18F97J94 FAMILY TABLE 31-5: Param No. DC CHARACTERISTICS: POWER-DOWN AND SUPPLY CURRENT PIC18F97J94 FAMILY (INDUSTRIAL) Device Typ(1) Max Units Conditions Module Differential Currents (ΔIWDT, ΔIBOR, ΔIHLVD, ΔIDSBOR, ΔIDSWDT, ΔIOSCB, ΔIADRC, ΔILCD, ΔIUSB) D020 (ΔIWDT) D021 (ΔIBOR) D022 (ΔIHLVD) Watchdog Timer 0.4 1 µA -40°C to +85°C 0.4 1 µA -40°C to +85°C VDD = 3.3V 4 8 µA -40°C to +85°C VDD = 2.0V 5 9 µA -40°C to +85°C VDD = 3.
PIC18F97J94 FAMILY TABLE 31-7: DC CHARACTERISTICS: POWER-DOWN AND SUPPLY CURRENT PIC18F97J94 FAMILY (INDUSTRIAL) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial DC CHARACTERISTICS Param No.
PIC18F97J94 FAMILY TABLE 31-8: DC CHARACTERISTICS: CTMU CURRENT SOURCE SPECIFICATIONS Standard Operating Conditions: 2V to 3.6V Operating temperature -40°C TA +85°C for Industrial DC CHARACTERISTICS Param Sym No. Min Typ(1) Max Units IOUT1 CTMU Current Source, Base Range — 550 — nA CTMUCON1<1:0> = 01 IOUT2 CTMU Current Source, 10x Range — 5.
PIC18F97J94 FAMILY TABLE 31-10: COMPARATOR SPECIFICATIONS Operating Conditions: 2.0V VDD 3.6V, -40°C TA +85°C Param No. Sym Characteristics Min Typ Max Units D300 VIOFF Input Offset Voltage — ±5.
PIC18F97J94 FAMILY TABLE 31-14: USB MODULE SPECIFICATIONS Operating Conditions: -40°C
PIC18F97J94 FAMILY 31.3 31.3.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC18F97J94 FAMILY 31.3.2 TIMING CONDITIONS The temperature and voltages specified in Table 31-15 apply to all timing specifications unless otherwise noted. Figure 31-2 specifies the load conditions for the timing specifications. TABLE 31-15: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Operating voltage VDD range as described in Section 31.1 and Section TABLE 311:.
PIC18F97J94 FAMILY 31.3.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 31-3: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 31-16: EXTERNAL CLOCK TIMING REQUIREMENTS Param. No. 1A Symbol FOSC Characteristic External CLKIN Frequency(1) Oscillator Frequency(1) 1 TOSC External CLKIN Period(1) Oscillator Period(1) Min Max Units Conditions DC 64 MHz EC Oscillator mode 4 16 MHz HS Oscillator mode 4 16 MHz HS + PLL Oscillator mode 15.
PIC18F97J94 FAMILY TABLE 31-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.0V TO 3.6V)(1) Param No. Sym F10 Min Typ Max FOSC Oscillator Frequency Range 4 — 16 MHz VDD = 2.0-3.6V, -40°C to +85°C F11 FSYS On-Chip VCO System Frequency 16 — 64 MHz VDD = 2.0-3.6V, -40°C to +85°C F12 trc PLL Start-up Time (Lock Time) — — 2 ms F13 CLK CLKOUT Stability (Jitter) -2 — +2 % Note 1: Characteristic Units Conditions These specifications are for x96 PLL or x8 PLL.
PIC18F97J94 FAMILY FIGURE 31-4: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 14 19 12 18 16 I/O Pin (Input) 15 17 I/O Pin (Output) New Value Old Value 20, 21 Note: Refer to Figure 31-2 for load conditions. TABLE 31-19: CLKO AND I/O TIMING REQUIREMENTS Param No.
PIC18F97J94 FAMILY FIGURE 31-5: PROGRAM MEMORY FETCH TIMING DIAGRAM (8-BIT) Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:8> Address Address 167 166 150 161 151 AD<7:0> Data Data Address Address 162 153 162A 154 155 BA0 163 170 170A ALE 168 CE OE Note: Fmax = 25 MHz in 8-Bit External Memory mode. TABLE 31-20: PROGRAM MEMORY FETCH TIMING REQUIREMENTS (8-BIT) Param No Symbol Characteristics Min Typ Max Units 150 TadV2aIL Address Out Valid to ALE (address setup time) 0.
PIC18F97J94 FAMILY FIGURE 31-6: PROGRAM MEMORY READ TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> BA0 AD<15:0> Address Address Address Data from External 150 151 Address 163 160 162 161 155 166 167 ALE 168 164 171 169 CE 171A OE 165 Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C unless otherwise stated. TABLE 31-21: CLKO AND I/O TIMING REQUIREMENTS Param. No Symbol Characteristics Min Typ Max Units 150 TadV2alL Address Out Valid to ALE (address setup time) 0.
PIC18F97J94 FAMILY FIGURE 31-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure 31-2 for load conditions. FIGURE 31-8: BROWN-OUT RESET TIMING BVDD VDD 35 VBGAP = 1.
PIC18F97J94 FAMILY FIGURE 31-9: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS For VDIRMAG = 1: VDD VHLVD (HLVDIF set by hardware) (HLVDIF can be cleared in software) VHLVD For VDIRMAG = 0: VDD HLVDIF TABLE 31-23: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial Param Sym No. D420 Characteristic Min Typ Max Units HLVD Voltage on VDD HLVDL<3:0> = 0100 Transition High-to-Low HLVDL<3:0> = 0101 2.
PIC18F97J94 FAMILY FIGURE 31-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS TxCKI 41 40 42 SOSCO/SCLKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 31-2 for load conditions. TABLE 31-24: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No.
PIC18F97J94 FAMILY FIGURE 31-11: CAPTURE/COMPARE/PWM TIMINGS (CCP1, CCP2 MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 Note: 54 Refer to Figure 31-2 for load conditions. TABLE 31-25: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1, CCP2 MODULES) Param Symbol No. 50 51 TCCL TCCH Characteristic Min Max Units CCPx Input Low No prescaler Time With prescaler 0.5 TCY + 20 — ns 10 — ns CCPx Input High Time 0.
PIC18F97J94 FAMILY FIGURE 31-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SCKx (CKPx = 0) 78 79 79 78 SCKx (CKPx = 1) 80 bit 6 - - - - - - 1 MSb SDOx LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure 31-2 for load conditions. TABLE 31-26: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No.
PIC18F97J94 FAMILY FIGURE 31-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) 81 SCKx (CKPx = 0) 79 73 SCKx (CKPx = 1) 80 78 MSb SDOx bit 6 - - - - - - 1 LSb bit 6 - - - - 1 LSb In 75, 76 SDIx MSb In 74 Note: Refer to Figure 31-2 for load conditions. TABLE 31-27: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No.
PIC18F97J94 FAMILY FIGURE 31-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SSx 70 SCKx (CKPx = 0) 83 71 72 78 79 79 78 SCKx (CKP = 1) 80 MSb SDOx bit 6 - - - - - - 1 LSb 75, 76 MSb In SDIx 77 bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure 31-2 for load conditions. TABLE 31-28: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param No.
PIC18F97J94 FAMILY FIGURE 31-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SSx SCKx (CKPx = 0) 70 83 71 72 SCKx (CKPx = 1) 80 MSb SDOx bit 6 - - - - - - 1 LSb 75, 76 SDIx MSb In 77 bit 6 - - - - 1 LSb In 74 Note: Refer to Figure 31-2 for load conditions. TABLE 31-29: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No.
PIC18F97J94 FAMILY I2C™ BUS START/STOP BITS TIMING FIGURE 31-16: SCLx 91 93 90 92 SDAx Stop Condition Start Condition Note: Refer to Figure 31-2 for load conditions. TABLE 31-30: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No.
PIC18F97J94 FAMILY FIGURE 31-17: I2C™ BUS DATA TIMING 103 102 100 101 SCLx 90 106 107 91 92 SDAx In 110 109 109 SDAx Out Note: Refer to Figure 31-2 for load conditions. TABLE 31-31: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. 100 Symbol THIGH 101 TLOW 102 TR Characteristic Clock High Time Clock Low Time Min Max Units 100 kHz mode 4.0 — s 400 kHz mode 0.6 — s MSSPx module 1.5 TCY — 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s MSSPx module 1.
PIC18F97J94 FAMILY MSSPx I2C™ BUS START/STOP BITS TIMING WAVEFORMS FIGURE 31-18: SCLx 93 91 90 92 SDAx Stop Condition Start Condition Note: Refer to Figure 31-2 for load conditions. TABLE 31-32: MSSPx I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol No.
PIC18F97J94 FAMILY TABLE 31-33: MSSPx I2C™ BUS DATA REQUIREMENTS Param. Symbol No. 100 101 THIGH TLOW Characteristic Min Max Units 100 kHz mode 2(TOSC)(BRG + 1) — — 400 kHz mode 2(TOSC)(BRG + 1) — — 1 MHz mode(1) 2(TOSC)(BRG + 1) — — Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — — 400 kHz mode 2(TOSC)(BRG + 1) — — (1) Clock High Time 2(TOSC)(BRG + 1) — — 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.
PIC18F97J94 FAMILY FIGURE 31-20: EUSARTx SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TXx/CKx pin 121 121 RXx/DTx pin 120 Note: 122 Refer to Figure 31-2 for load conditions. TABLE 31-34: EUSARTx/AUSARTx SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
PIC18F97J94 FAMILY TABLE 31-36: A/D CONVERTER CHARACTERISTICS: PIC18F97J94 (INDUSTRIAL) Param No. Sym Characteristic Min Typ Max Units Conditions VREF 2.0V A01 NR Resolution — — 12 bit A03 EIL Integral Linearity Error — <±1 ±2.0 LSB A04 EDL Differential Linearity Error — <±1 +2.0/-1.0 LSB VDD = 3.0V (VREF 2.0V) A06 EOFF Offset Error — <±1 ±5 LSB VDD = 3.0V (VREF 2.0V) A07 EGN Gain Error — <±1 ±5 LSB VDD = 3.0V (VREF 2.
PIC18F97J94 FAMILY FIGURE 31-22: A/D CONVERSION TIMING BSF ADCON1L, SAMP (Note 2) 131 Q4 130 132 A/D CLK 11 A/D DATA 10 9 ... ... 2 1 0 NEW_DATA OLD_DATA ADRES TCY (Note 1) ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
PIC18F97J94 FAMILY NOTES: DS30575A-page 662 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 32.0 PACKAGING INFORMATION 32.1 Package Marking Information 64-Lead QFN (9x9x0.9 mm) PIN 1 Example PIN 1 XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 64-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 80-Lead TQFP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 100-Lead TQFP (12x12x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY 100-Lead TQFP (14x14x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: DS30575A-page 664 Example PIC18F97J94I/PF e3 1210017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free.
PIC18F97J94 FAMILY 32.2 Package Details The following sections give the technical details of the packages. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30575A-page 666 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 E e E1 N b NOTE 1 123 NOTE 2 α A φ c A2 β A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV 0,//,0(7(56 0,1 1 120 0$; /HDG 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ± )RRW /HQJ
PIC18F97J94 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 E e E1 N b NOTE 1 12 3 α NOTE 2 A c β φ A2 A1 L1 L 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV 0,//,0(7(56 0,1 1 120 0$; /HDG 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ± )RRW
PIC18F97J94 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 e E E1 N b NOTE 1 1 23 NOTE 2 α c A φ L β A1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV A2 L1 0,//,0(7(56 0,1 1 120 0$; /HDG 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ± )RRW
PIC18F97J94 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 3) ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 e E1 E b N α NOTE 1 1 23 A NOTE 2 φ c β A2 A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV 0,//,0(7(56 0,1 1 120 0$; /HDG 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ± )RRW
PIC18F97J94 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY NOTES: DS30575A-page 676 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY APPENDIX A: REVISION HISTORY Revision A (October 2012) Original data sheet for PIC18F97J94 family devices. 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY NOTES: DS30575A-page 678 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY INDEX Numerics 12-Bit A/D Converter with Threshold Scan ...................... 435 A A/D A/D Module State Machine Module ......................... 457 Conversion Requirements ....................................... 661 Converter Characteristics ........................................ 660 Registers .................................................................. 437 Absolute Maximum Ratings ............................................. 629 AC (Timing) Characteristics ..................
PIC18F97J94 FAMILY BTG .................................................................................. 589 BZ ..................................................................................... 590 C C Compilers MPLAB C18 ............................................................. 626 CALL ................................................................................ 590 CALLW ............................................................................. 619 Capture (CCP Module) ...................
PIC18F97J94 FAMILY Oscillator Options and Features .................................. 9 CPFSEQ .......................................................................... 592 CPFSGT .......................................................................... 593 CPFSLT ........................................................................... 593 Customer Change Notification Service ............................ 691 Customer Notification Service .......................................... 691 Customer Support .
PIC18F97J94 FAMILY External Clock Input ........................................................... 52 External Memory Bus ....................................................... 153 16-Bit Byte Select Mode .......................................... 159 16-Bit Byte Write Mode ............................................ 157 16-Bit Data Width Modes ......................................... 156 16-Bit Mode Timing .................................................. 160 16-Bit Word Write Mode ...................
PIC18F97J94 FAMILY Instruction Cycle .............................................................. 118 Clocking Scheme ..................................................... 118 Flow/Pipelining ......................................................... 118 Instruction Set .................................................................. 575 ADDLW .................................................................... 581 ADDWF ....................................................................
PIC18F97J94 FAMILY M Master Synchronous Serial Port (MSSP). See MSSP. Memory Organization ....................................................... 113 Data Memory ........................................................... 120 Program Memory Maps ........................................... 113 Memory Programming Requirements .............................. 637 Microchip Internet Web Site ............................................. 691 MOVF ....................................................................
PIC18F97J94 FAMILY Extended Instruction Set .......................................... 138 Hard Memory Vectors .............................................. 114 Instructions ............................................................... 119 Two-Word ........................................................ 119 Interrupt Vector ........................................................ 114 Look-up Tables ........................................................ 117 Organization ................................
PIC18F97J94 FAMILY ECCPxAS (ECCPx Auto-Shutdown Control) ........... 331 ECCPxDEL (Enhanced PWM Control) .................... 334 EECON1 (EEPROM Control 1) ................................ 145 HLVDCON (High/Low-Voltage Detect Control) ........ 501 HOUR (Hour Value) ................................................. 305 INTCON (Interrupt Control) ...................................... 170 INTCON2 (Interrupt Control 2) ................................. 171 INTCON3 (Interrupt Control 3) ........................
PIC18F97J94 FAMILY Associated Alarm Value Registers ........................... 316 Associated Control Registers ................................... 316 Associated Value Registers ..................................... 316 Control Registers ..................................................... 299 Operation ................................................................. 310 Calibration ........................................................ 313 Clock Source ................................................
PIC18F97J94 FAMILY CLKO and I/O .......................................................... 644 Clock Jitter Causing Pulse Between Consecutive Zeros ................................................................ 433 Clock Synchronization ............................................. 391 Clock Transition ......................................................... 58 Clock/Instruction Cycle ...................................... 38, 118 Converting 1 Channel 16 Times per Interrupt ..........
PIC18F97J94 FAMILY Example SPI Slave Mode Requirements (CKE = 1) 654 External Clock Requirements .................................. 642 HLVD Characteristics ............................................... 648 I2C Bus Data Requirements (Slave Mode) .............. 656 I2C Bus Start/Stop Bits Requirements (Slave Mode) ................................................... 655 Internal RC Accuracy (INTOSC) .............................. 643 MSSPx I2C Bus Data Requirements ........................
PIC18F97J94 FAMILY NOTES: DS30575A-page 690 2012 Microchip Technology Inc.
PIC18F97J94 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC18F97J94 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC18F97J94 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device PIC18F97J94, PIC18F96J94, PIC18F95J94, PIC18F87J94, PIC18F86J94, PIC18F85J94, PIC18F67J94, PIC18F66J94, PIC18F65J94 VDD range 2.0 to 3.
PIC18F97J94 FAMILY NOTES: DS30575A-page 694 2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.