User manual
PICDEM™ Lab II Development Board User’s Guide
DS40001814A-page 28 2015 Microchip Technology Inc.
FIGURE A-2: PICDEM™ LAB II DEVELOPMENT BOARD SCHEMATIC 2
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
* of *
PICdem Lab 2
11/25/2014 9:48:47 AM
219-0544 Sheet 2.SchDoc
Project Title
Sch #: Date:
File:
Revision: Sheet
Designed with
Drawn By:
219-0544
Sheet Title
**
Engineer:
219-0544
03-219-0544
ProjectRevisionSCH
Size
B
219-0544
PartNumber:
Altium.com
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8
9
10
16
1514
13
12
11
17
1
2
3
19
18
20
21
22
23
24
25
26
27
28
110-91-328-41-001
U4
4
5
6
7
8
9
10
16
15
14
13
12
11
17
1
2
3
19
18
20 21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
110-93-640-41-001050
U5
4
5
6
7
8
9
10
16
15
14
13
12
11
17
1
2
3
19
18
20
110-91-320-41-001
U3
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RB0
RB1
RB2
RB3
RB4
RB5
ICSPCLK4
ICSPDAT4
RC0
RC1
RC2
RC3 RC4
RC5
RC6
RC7
VPP4
RA0
RA1
RA2
RA3
RA4
RA5
RB0
RB1
RB2
RB3
RB4
RB5
ICSPCLK4
ICSPDAT4
RC0
RC1
RC2
RC3 RC4
RC5
RC6
RC7
RD0
RD1 RD2
RD3
RD4
RD5
RD6
RD7
RE0
RE1
RE2
VPP4
RA6
RA7
VDD4
VDD4
0.1uF
25V
0603
C20
SGND
4
5
6
7
8
9 10
16
15
14
13
12
11
17
1
2
3
18
110-99-318-41-001
U2
2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
1
17 18
19 20
J20
2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
1
17 18
19 20
J19
2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
1
17 18
J15
2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
1
17 18
J14
PIC10F200-I/P
VDD
2
VSS
7
GP3/MCLR/VPP
8
GP0/ICSPDAT/CIN+
5
GP1/ICSPCLK/CIN-
4
GP2/T0CKI/COUT/FOSC4
3
U1
1 2
3 4
5 6
7 8
J13
1 2
3 4
5 6
7 8
J12
ICSPCLK1
U1_GP2
VPP1
ICSPDAT1
U1_GP2
VPP1
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
J21
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
J23
RB0
RB1
RB2
RB3
RB4
RB5
RC4
RC5
RC6
RC7
RD2
RD3
RD4
RD5
RD6
RD7
VDD4 VDD4
RA0
RA1
RA2
RA3
RA4
RA5
RC0
RC1
RC2
RC3
RD0
RD1
RE0
RE1
RE2
VPP4
RA6
RA7
0.1uF
25V
0603
C21
SGND
0.1uF
25V
0603
C22
SGND
0.1uF
25V
0603
C23
SGND
0.1uF
25V
0603
C24
SGND
0.1uF
25V
0603
C25
SGND
VDD1
VDD2
VDD3
VDD4
VDD4
VDD3
SGND
VDD1
VDD2
VDD1VDD1
ICSPCLK2
ICSPCLK3
ICSPCLK4
ICSPCLK1
ICSPCLK1
U1_GP2
ICSPDAT1
ICSPDAT2
ICSPDAT3
ICSPDAT4
1
2
3
4
5
6
HDR-2.54 Male 1x6
ICSP1
VDD1
VPP1
ICSPCLK1
ICSPDAT1
SGND
1
2
3
4
5
6
HDR-2.54 Male 1x6
ICSP2
VPP2
VDD2
ICSPDAT2
ICSPCLK2
SGND
1
2
3
4
5
6
HDR-2.54 Male 1x6
ICSP3
VPP3
VDD3
ICSPDAT3
ICSPCLK3
SGND
1
2
3
4
5
6
HDR-2.54 Male 1x6
ICSP4
VPP4
VDD4
ICSPDAT4
ICSPCLK4
SGND
ICSPDAT2
ICSPCLK2
VPP2
U2_RA0
U2_RA1U2_RA2
U2_RA3
U2_RA4
U2_RB0
U2_RB1
U2_RB2
U2_RB3 U2_RB4
U2_RB5
VPP2
U2_RA2
U2_RA3
U2_RA4
U2_RB0
U2_RB1
U2_RB2
U2_RB3
U2_RA6
U2_RA7
U2_RB4
U2_RB5
U2_RA0
U2_RA1
U2_RA6
U2_RA7
ICSPDAT3
ICSPCLK3
U3_RB4
U3_RB5
U3_RB6U3_RB7
U3_RC0
U3_RC1
U3_RC2U3_RC3
U3_RC4
U3_RC5
U3_RA2VPP3
U3_RA4
U3_RA5
U3_RB4
U3_RB5
U3_RB6
U3_RC0
U3_RC1
U3_RC2
U3_RA2
U3_RC6
U3_RC7
U3_RA5
U3_RB7
U3_RC3
U3_RC4
U3_RC5
VPP3
U3_RA4
U3_RC6
U3_RC7
SGND
SGND
SGND
SGND
SGND
SGND
SGND
SGND
VPP1