Datasheet

 2012-2013 Microchip Technology Inc. Advance Information DS40001667C-page 33
MGC3130
7.0 HARDWARE INTEGRATION
7.1 ESD Considerations
The MGC3130 provides Electrostatic Discharge (ESD)
Voltage protection up to 2 kV (HBM). Additional ESD
countermeasures may be implemented individually to
meet application-specific requirements.
7.2 Power Noise Considerations
MGC3130 filtering capacitors are included in the
reference design schematic (Please refer to Figure 7-1).
7.3 Irradiated High-Frequency Noise
In order to suppress irradiated high-frequency signals,
the five Rx channels of the chip are connected to the
electrodes via serial 10 kresistors, as close as possi-
ble to MGC3130. The 10 k resistor and the MGC3130
input capacitance are building a low-pass filter with a
corner frequency of 3 MHz.
7.4 Standard Schematic
(3.3V V
DD  3.465V)
A standard application schematic for the 28-lead QFN
package pinout is depicted below in Figure 7-1. For
more details, please refer to Figure 1.
FIGURE 7-1: STANDARD SCHEMATIC FOR 3.3V  VDD  3.465V VOLTAGE RANGE
MGC3130
VDD
VSS1
VSS3
VDD
100 nF
4.7 μF 4.7 μF
IS2
MCLR
SI0
SI1
EIO0
SDA
SCL
GPIO/IRQ
HOST
VDD
1.8 kΩ
1.8 kΩ
RESET
10 kΩ
VDD
TXD
RX0
RX1
RX2
RX3
RX4
VDD
VINDS
VCAPS
VCAPA
VCAPD
EXP
VSS1
NC
NC
NC
VSS2
EIO7 EIO1 EIO6
NC
North Electrode
South Electrode
East Electrode
WestElectrode
Center Electrode
IS1
IS2
R9 (10 kΩ)
C1
C3
C2
R1
R2
R3
10 kΩ 10 kΩ
10 kΩ 10 kΩ
IS1
IS2
VDD VDD
R6 R8
R5 (n.p) R7 (n.p)
R10 (10 kΩ)
R11 (10 kΩ)
R12 (10 kΩ)
R13 (10 kΩ)
VDD
10 kΩ
R4
EIO2 EIO3
n.p: not populated
Gesture Port
EIO7
EIO1 EIO6 EIO2 EIO3
Interface Selection
Note: R5 and R7 are not populated.