Datasheet

MGC3130 DS40001667C-page 32 Advance Information  2012-2013 Microchip Technology Inc.
FIGURE 6-4: I
2
C™ MASTER READ BIT TIMING DIAGRAM
FIGURE 6-5: I
2
C™ MASTER WRITE BIT TIMING DIAGRAM
312 456789 312 456789 312 456789
A7 A6 A5 A4 A3 A2 A1
1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Address R/W ACK ACK ACKData Data
Address Bits Latched in Data Bits Valid Out Data Bits Valid Out
SCL may be stretched SCL may be stretched
S
P
Start Bit
Stop Bit
SDA
SCL
312 456789 312 456789 312 456789
A7 A6 A5 A4 A3 A2 A1
0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Address R/W ACK ACK ACKData Data
Address Bits Latched in Data Bits Valid Out Data Bits Valid Out
SCL may be stretched SCL may be stretched
S
P
Start Bit
Stop Bit
SDA
SCL