Datasheet

 2012-2013 Microchip Technology Inc. Advance Information DS40001667C-page 31
MGC3130
6.6.3 SPI
SPI features:
• One Port: SCLK, CS, MOSI, MISO
• Master and Slave mode
• Up to 3 MHz
• Support of all clock edge and polarity options
SPI Hardware Interface
A summary of the hardware interface pins is shown
below in Table 6 - 1 0 .
• SCLK Pin:
- The MGC3130 controller’s SCLK pin drives
the communication bus clock.
- The Idle state of the SCLK should be low.
- Data is transmitted on the falling edge of
SCLK.
•MOSI Pin:
- The MGC3130 controller’s MOSI pin sends/
reads serial data to/from the slave/host.
•MISO Pin:
- The MGC3130 controller’s MISO pin reads/
sends serial data from/to the slave/host.
•CS
Pin:
- The MGC3130 controller’s CS
pin provides
device selection functionality.
Note: Currently, only single-zone I
2
C™ Slave
mode with I
2
C0 is supported. Other
modes are planned for future releases of
GestIC
®
Library. Please contact your
Microchip representative for further
details.
TABLE 6-10: SPI PIN DESCRIPTION
MGC3130 Pin Description
SCLK Master Clock
CS
Chip Select
MISO Master Input Slave Output
MOSI Master Output Slave Input
TABLE 6-11: SPI CS PIN DESCRIPTION
CS Pin Description
V
SS Active
VDD Inactive