Datasheet

 2012-2013 Microchip Technology Inc. Advance Information DS40001667C-page 29
MGC3130
6. I
2
C master receives eight data bits (MSB first)
presented on SDA by the MGC3130, at eight
sequential I
2
C master clock (SCL) cycles. The
data is latched out on SCL falling edges to
ensure it is valid during the subsequent SCL
high time.
7. If data transfer is not complete, then:
-I
2
C master acknowledges (ACK) reception of
the eight data bits by presenting a low on
SDA, followed by a low-high-low on SCL.
- Go to step 5.
8. If data transfer is complete, then:
-I
2
C master acknowledges (ACK) reception of
the eight data bits and a completed data
transfer by presenting a high on SDA,
followed by a low-high-low on SCL.
I
2
C Master Write Bit Timing (MGC3130 Slave)
I
2
C master write is to send supported commands to the
MGC3130. The timing diagram is shown in Figure 6-5.
• Address bits are latched into the MGC3130 on the
rising edges of SCL.
• Data bits are latched into the MGC3130 on the
rising edges of SCL.
• ACK bit:
- MGC3130 presents the ACK bit on the ninth
clock for address acknowledgment
-I
2
C master presents the ACK bit on the ninth
clock for data acknowledgment
• The master must monitor the SCL pin prior to
asserting another clock pulse, as the MGC3130
may be holding off the master by stretching the
clock.
I
2
C Communication Steps
1. SCL and SDA lines are Idle high.
2. I
2
C master presents Start bit to the MGC3130 by
taking SDA high-to-low, followed by taking SCL
high-to-low.
3. I
2
C master presents 7-bit address, followed by a
R/W
= 0 (Write mode) bit to the MGC3130 on
SDA, at the rising edge of eight master clock
(SCL) cycles.
4. MGC3130 compares the received address to its
Device ID. If they match, the MGC3130
acknowledges (ACK) the I
2
C master sent
address by presenting a low on SDA, followed
by a low-high-low on SCL.
5. I
2
C master monitors SCL, as the MGC3130 may
be clock stretching, holding SCL low to indicate
the I
2
C master should wait.
6. I
2
C master presents eight data bits (MSB first) to
the MGC3130 on SDA, at the rising edge of
eight master clock (SCL) cycles.
7. MGC3130 acknowledges (ACK) receipt of the
eight data bits by presenting a low on SDA, fol-
lowed by a low-high-low on SCL.
8. If data transfer is not complete, then go to step
5.
9. Master presents a Stop bit to the MGC3130 by
taking SCL low-high, followed by taking SDA
low-to-high.
6.6.2 TRANSFER STATUS LINE
MGC3130 requires a dedicated Transfer Status line
(TS) which features a data transfer status function. It is
used by both I
2
C Master and Slave to control data flow.
The TS (Transfer Status) line is electrically open-drain
and requires a pull-up resistor of typically 10 k, from
TS to V
DD. TS Idle state is high.
The MGC3130 (I
2
C Slave) uses this line to inform the
host controller (I
2
C Master) that there is data available
which can be transferred. The host controller uses the
TS line to indicate that data is being transferred and
prevents MGC3130 from updating its data buffer.
Table 6-9 shows how the TS line is used in the different
states of communication.