Datasheet

MGC3130
DS40001667C-page 28 Advance Information  2012-2013 Microchip Technology Inc.
6.6 Communication Interfaces
6.6.1 I
2
C
The MGC3130 supports two I
2
C interfaces. Only I
2
C0
is used in a single-zone configuration.
I
2
C0 and I
2
C1 features:
• Two ports: SCL0, SDA0 and SCL1, SDA1
• Master and Slave mode
• Up to 400 kHz
• 7-bit Addressing mode
• Hardware state machine for basic protocol
handling
• Support for repeated start and clock stretching
(Byte mode)
• No multi-master support
I
2
C Hardware Interface
A summary of the hardware interface pins is shown
below in Table 6 - 5 .
•SCL Pin
- The SCL (Serial Clock) pin is electrically
open-drain and requires a pull-up resistor of
typically 1.8 kΩ (for a maximum bus load
capacitance of 200 pF), from SCL to V
DD.
SCL Idle state is high.
•SDA Pin
- The SDA (Serial Data) pin is electrically
open-drain and requires a pull-up resistor of
typically 1.8 kΩ (for a maximum bus load
capacitance of 200 pF), from SDA to V
DD.
- SDA Idle state is high.
- Master write data is latched in on SCL rising
edges.
- Master read data is latched out on SCL falling
edges to ensure it is valid during the
subsequent SCL high time.
I
2
C Addressing:
The MGC3130 Device ID 7-bit address is: 0x42
(0b1000010) or 0x43 (0b1000011) depending on the
interface selection pin configuration (IS2). Please refer
to Table 6 - 6 .
I
2
C Master Read Bit Timing (MGC3130 I
2
C Slave)
Master read is to receive position data, gesture reports
and command responses from the MGC3130. The
timing diagram is shown in Figure 6-4.
• Address bits are latched into the MGC3130 on the
rising edges of SCL.
• Data bits are latched out of the MGC3130 on the
rising edges of SCL.
• ACK bit:
- MGC3130 presents the ACK bit on the ninth
clock for address acknowledgment
-I
2
C master presents the ACK bit on the ninth
clock for data acknowledgment
•The I
2
C master must monitor the SCL pin prior to
asserting another clock pulse, as the MGC3130
may be holding off the I
2
C master by stretching
the clock.
I
2
C Communication Steps
1. SCL and SDA lines are Idle high.
2. I
2
C master presents Start bit to the MGC3130 by
taking SDA high-to-low, followed by taking SCL
high-to-low.
3. I
2
C master presents 7-bit address, followed by a
R/W
= 1 (Read mode) bit to the MGC3130 on
SDA, at the rising edge of eight master clock
(SCL) cycles.
4. MGC3130 compares the received address to its
Device ID. If they match, the MGC3130
acknowledges (ACK) the master sent address
by presenting a low on SDA, followed by a low-
high-low on SCL.
5. I
2
C master monitors SCL, as the MGC3130 may
be clock stretching, holding SCL low to indicate
that the I
2
C master should wait.
TABLE 6-5: I
2
C™ PIN DESCRIPTION
MGC3130 Pin Multiplexed Functions
SCL Serial Clock to Master I
2
C™
SDA Serial Data to Master I
2
C™
TABLE 6-6: I
2
C™ DEVICE ID ADDRESS
Device ID Address, 7-bit
A6 A5 A4 A3 A2 A1 A0
100001IS2
TABLE 6-7: I
2
C™ DEVICE WRITE ID
ADDRESS (0x84 OR 0x86)
I
2
C™ Device Write ID Address
A7 A6 A5 A4 A3 A2 A1 A0
100001IS2 0
TABLE 6-8: I
2
C™ DEVICE READ ID
ADDRESS (0x85 OR 0x87)
I
2
C™ Device Read ID Address
A7 A6 A5 A4 A3 A2 A1 A0
100001IS2 1