Datasheet

MGC3130
DS40001667C-page 16 Advance Information  2012-2013 Microchip Technology Inc.
Standard applications (without STEP-UP) (3.3V  VDD
 3.465V):
The system starts when (see Figure 4-5):
• Power-up/Time-out period (t
PWRT
) is elapsed
•V
DD = 3.3V is already reached before the end of
t
PWRT
timing
The power-up sequence begins by increasing the
voltage on the V
DD pin (from 0V). If the slope of the VDD
rise time is faster than 4.5 V/ms, the system starts
correctly.
If the slope is less than 4.5 V/ms, the MCLR
pin must
be held low, by external circuitry, until a valid operating
VDD level is reached.
FIGURE 4-5: POWER SUPERVISORS
MCLR
1.5V
V
DD
time
3.3V
t1: t
RSTDLY
: Reset delay typically 200 μs, 120 μs minimum
t2: t
PWRT
: Power-up Time-out
2V
t1
t2