Datasheet

2012-2013 Microchip Technology Inc. Advance Information DS40001667C-page 15
MGC3130
4.2.2 POWER SUPERVISORS
During the Power-up sequence, the system is kept
under Reset condition for approximately 200 µs (Reset
delay: t
RSTDLY
) after the VDD =1.5V voltage is reached
(1.2V minimum). During this delay, the system Reset
will remain low and the VDD should reach typically 2V.
When the Reset delay is elapsed, the system Reset is
released (high) and the system starts Power-up/Time-
out (t
PWRT
) sequence. The system start depends on
the target application (if the STEP-UP will be used or
not) and on the used V
DD voltage. The Power-up/Time-
out period (t
PWRT
) after Reset takes 36 LSO cycles.
(see Table 4 - 3).
STEP-UP applications (2.5V
VDD < 3.3V):
The system starts when (see Figure 4-5):
Power-up/Time-out period (t
PWRT
) is elapsed
•V
DD = 2.5V is already reached before the end of
t
STEP-UP
during the t
PWRT
(See Table 4-3). 2.5V is
the minimum voltage needed to power the
STEP-UP.
The STEP-UP converter starts automatically from 2.5V
if the external STEP-UP components are assembled. It
stays activated until a 3.465V V
DD voltage level is
reached.
For V
DD input beyond this level, the STEP-UP
converter will automatically stop operating and the
GestIC Library can disable it. For more details, please
refer to Figure 4-5.
The power-up sequence begins by increasing the
voltage on the V
DD pin (from 0V). If the slope of the VDD
rise time is faster than 6 V/ms, the system starts
correctly.
If the slope is less than 6 V/ms, the MCLR
pin should
be held low, by external circuitry, until a valid operating
VDD level is reached.
FIGURE 4-4: STEP-UP APPLICATIONS START-UP
MCLR
STEP-UP
1.5V
V
STEP-UP
VDD
2.5V
time
3.465V
3.3V
t1: t
RSTDLY
: Reset delay typically 200 μs, 120 μs minimum
t2: t
PWRT
: Power-up Time-out
2V
t1
t2
Hysteresis