Datasheet

MGC3130
DS40001667C-page 14 Advance Information  2012-2013 Microchip Technology Inc.
4.1 Reset Block
The Reset block combines all Reset sources. It
controls the device system’s Reset signal (SYSRST).
The following is a list of device Reset sources:
•MCLR
: Master Clear Reset pin
• SWR: Software Reset available through GestIC
Library
• WDTR: Watchdog Timer Reset
A simplified block diagram of the Reset block is
illustrated in Figure 4-2.
FIGURE 4-2: SYSTEM RESET BLOCK
DIAGRAM
4.2 Power Control and Clocks
4.2.1 POWER MANAGEMENT UNIT (PMU)
The device requires a 3.3V ±5% supply voltage at VDD.
Enabling the internal STEP-UP converter extends the
voltage range to 2.5 to 3.465V.
According to Figure 4-3, the used power domains are
as follows:
• V
DD Domain: This domain is powered by
V
DD = 2.5V to 3.465V (typical VDD = 3.3V). VDD is
the external power supply for EIO, wake-up logic,
WDTR, internal regulators and STEP-UP
converter. It is provided externally through the
V
DD pin.
• V
DDC Domain: This domain is powered by
V
DDC = 1.8V. It is generated by an embedded low-
impedance and fast linear voltage regulator. The
voltage regulator is working under all conditions
(also during Deep Sleep mode) preserving the
MGC3130 data context. V
DDC is the internal
power supply voltage for digital blocks, Reset
block and RC oscillators. An external block
capacitor, C
EFCD, is required on VCAPD pin.
• V
DDA Domain: This domain is powered by
V
DDA = 3.0V. It is generated by an embedded low-
impedance and fast linear voltage regulator.
During Deep Sleep mode, the analog voltage
regulator is switched off. V
DDA is the internal
analog power supply voltage for the ADCs and
the signal conditioning. An external block
capacitor, C
EFCA, is required on VCAPA pin.
• V
DDM Domain: This domain is powered by
V
DDM = 3.3V. VDDM is the internal power supply
voltage for the internal Flash memory. This power
supply is depending on VDD voltage range. If
V
DD ≥ 3.3V, the memory is directly powered
through the V
DD pin. In case of VDD < 3.3V, the
Flash power supply is generated internally by an
embedded STEP-UP converter.
FIGURE 4-3: POWER SCHEME BLOCK
DIAGRAM
• STEP-UP Converter: The STEP-UP converter is
generating 3.3V from the connected supply
voltage V
DD (if it is lower than 3.3V). This voltage
is required by the internal Flash memory. The
required voltage reference is taken from the
voltage reference block. During Deep Sleep
mode, the converter is switched off. It requires an
external connected inductor, a filtering capacitor
and a Schottky diode connected to the V
INDS and
V
CAPS pins. If the supply voltage is high enough,
the STEP-UP converter will be disabled. Please
refer to Section 9.0 “Electrical Specifications”
for more details.
MCLR
Glitch Filter
Deep sleep
WDTR
Software Reset (SWR)
WDT Time-out
SYSRST
SPU
Digital
Peripherals
Reset Block
Internal Osc.
VDDC Domain
Analog voltage
regulator
Digital voltage
regulator
Flash
Memory
Wake-up logic
WDTR
EIO
VDDM Domain
STEP-UP converter
VCAPS
VSS2
VDD
VSS1
V
CAPA
V
SS3
ADC
Signal Conditioning Blocks
VDDA Domain
VCAPD
VINDS
VDD Domain