User's Manual

Table Of Contents
© 2014 Microchip Technology Inc. Preliminary DS60001270C-page 11
CY920
TABLE 1-8: UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART)
TABLE 1-9: AUDIO
Signal Type Description
UART_RXD1 I UART1 input to the DM920, used for shell access. Microchip recommends
providing a connection to an external RS-232 transceiver and a DB9 connector to
connect to a PC COM port. This connection can be used for the product
development debugging, module programming control on the product
manufacturing line, and module control during certification procedures.
UART_TXD1 O UART1 output from the DM920, used for shell access. Microchip recommends
providing a connection to an external RS-232 transceiver and a DB9 connector to
connect to a PC COM port. This connection can be used for the product
development debugging, module programming control on the product
manufacturing line, and module control during certification procedures.
UART_RXD0 I UART0 input, used for Bluetooth (BT) in BT SKU. It can be used as an additional
UART in non-BT SKU.
UART_TXD0 O UART0 output, used for Bluetooth in case of BT SKU. It can be used as an
additional UART in non-BT SKU
Legend: O = Output I /O = Input /Output I = Input P = Power
Signal Type Description
AV2DATA0
AV2DATA2
AV2DATA3
OI
2
S or left justified audio data output. It is typically connected to an external D/A
converter input or an external DSP for further audio processing.
AV2DATA0 is used for the main left and right channel audio output data. AV2DATA2
and AV2DATA3 may be used for surround sound rear channels and sub-woofer.
See Note 1.
AV2DATA1
II
2
S or left justified audio data input. It can be driven from an optional external A/D
converter used to interface to iPod analog output or other analog audio sources, or
aux in jack. If not used, leave it open.
AV2CTRL0 O LRCK, audio data word clock at the audio sample rate (Fs) (currently, maximum
supported frequency is 192 kHz).
AV2CTRL1 O MCLK, audio master clock at 256 Fs. It can be used to clock an external D/A
converter or an external DSP. The Fs multiplier may vary at sample rates more than
48 kHz.
AV2CLK O SCLK, audio data bit clock at 64 Fs. It allows up to 32 audio data bits per sample
word.
AV4DATA0 O SPDIF format output. It can support sample rate up to 192 kHz. Consequently, the
maximum instantaneous frequency on this pin is 24.576 MHz.
AV4DATA1 I SPDIF input. Currently it is not used, do not connect.
AV3DATA0
AV3DATA1
I/O Used for I
2
S or left justified audio data, depend on firmware and use case. The AV3
port control and clock signals are defined as GPIOs, see Table 1-15. If required,
succeeding use cases may use AV3 control and clock signals as audio clocks.
Legend: O = Output I /O = Input /Output I = Input P = Power
Note 1:
For the audio port timing diagrams, setup and hold timing details, refer to the
“DM920 Data Sheet”
(DS60001278)
.