Datasheet

78
XMEGA D4 [DATASHEET]
8135P–AVR–01/2014
Figure 32-4. TOSC input capacitance.
The parasitic capacitance between the TOSC pins is C
L1
+ C
L2
in series as seen from the crystal when oscillating without
external capacitors.
32.1.14 SPI Characteristics
Figure 32-5. SPI timing requirements in master mode.
C
L1
C
L2
2CS
O
T
1
CS
O
T
Device internal
External
32.768kHz crystal
MSB LSB
BSLBSM
t
MOS
t
MIS
t
MIH
t
SCKW
t
SCK
t
MOH
t
MOH
t
SCKF
t
SCKR
t
SCKW
MOSI
(Data Output)
MISO
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS