Datasheet

75
XMEGA D4 [DATASHEET]
8135P–AVR–01/2014
32.1.13.5 Internal Phase Locked Loop (PLL) characteristics
Table 32-23. Internal PLL characteristics.
Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
32.1.13.6 External clock characteristics
Figure 32-3. External clock drive waveform.
Table 32-24. External clock
(1)
.
Notes: 1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
2. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
Symbol Parameter Condition Min. Typ. Max. Units
f
IN
Input frequency Output frequency must be within f
OUT
0.4 64
MHz
f
OUT
Output frequency
(1)
V
CC
= 1.6 - 1.8V 20 48
V
CC
= 2.7 - 3.6V 20 128
Start-up time 25
µs
Re-lock time 25
t
CH
t
CL
t
CK
t
CH
V
IL1
V
IH1
t
CR
t
CF
Symbol Parameter Condition Min. Typ. Max. Units
1/t
CK
Clock frequency
(2)
V
CC
= 1.6 - 1.8V 0 90
MHz
V
CC
= 2.7 - 3.6V 0 142
t
CK
Clock period
V
CC
= 1.6 - 1.8V 11
ns
V
CC
= 2.7 - 3.6V 7.0
t
CH/CL
Clock high/low time
V
CC
= 1.6 - 1.8V 4.5
V
CC
= 2.7 - 3.6V 2.4
V
IL/IH
Low/high level input voltage See Table 32-7 on page 68 V
t
CK
Reduction in period time from one
clock cycle to the next
10 %