Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller VQFN 44 (7x7) 8/16-Bit 32 MHz I/O number 34

8135P–AVR–01/2014

Features

 High-performance, low-power Atmel

AVR

XMEGA

8/16-bit Microcontroller

 Nonvolatile program and data memories

 16K - 128KBytes of in-system self-programmable flash

 4K - 8KBytes boot section

 1K - 2KBytes EEPROM

 2K - 8KBytes internal SRAM

 Peripheral Features

 Four-channel event system

 Four 16-bit timer/counters

 Two timer/counters with 4 output compare or input capture channels

 Two timer/counters with 2 output compare or input capture channels

 High-resolution extensions on all timer/counters

 Advanced waveform extension (AWeX) on one timer/counter

 Two USARTs with IrDA support for one USART

 Two Two wire interfaces with dual address match (I

C and SMBus compatible)

 Two serial peripheral interfaces (SPIs)

 CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3) generator

 16-bit real time counter (RTC) with separate oscillator

 One twelve-channel, 12-bit, 200ksps Analog to Digital Converter

 Two Analog Comparators with window compare function, and current sources

 External interrupts on all general purpose I/O pins

 Programmable watchdog timer with separate on-chip ultra low power oscillator

 QTouch

library support

 Capacitive touch buttons, sliders and wheels

 Special microcontroller features

 Power-on reset and programmable brown-out detection

 Internal and external clock options with PLL and prescaler

 Programmable multilevel interrupt controller

 Five sleep modes

 Programming and debug interfaces

 PDI (program and debug interface)

 I/O and packages

 34 Programmable I/O pins

 44 - lead TQFP

 44 - pad VQFN/QFN

 49 - ball VFBGA

 Operating voltage

 1.6 – 3.6V

 Operating frequency

 0 – 12MHz from 1.6V

 0 – 32MHz from 2.7V

8/16-bit Atmel XMEGA D4 Microcontroller

ATxmega128D4 / ATxmega64D4 /

ATxmega32D4 / ATxmega16D4

Summary of content (324 pages)

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8/16-bit Atmel XMEGA D4 Microcontroller ATxmega128D4 / ATxmega64D4 / ATxmega32D4 / ATxmega16D4 Features  High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller  Nonvolatile program and data memories 16K - 128KBytes of in-system self-programmable flash 4K - 8KBytes boot section  1K - 2KBytes EEPROM  2K - 8KBytes internal SRAM    Peripheral Features             Four-channel event system Four 16-bit timer/counters  Two timer/counters with 4 output compare or input capt
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1.
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2. Pinout/Block diagram Figure 2-1.
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Figure 2-2.
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3. Overview The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA device achieves throughputs CPU approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. The AVR CPU combines a rich instruction set with 32 general purpose working registers.
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3.1 Block Diagram Figure 3-1. XMEGA D4 Block Diagram Digital function Programming, debug, test Analog function Oscillator/Crystal/Clock General Purpose I/O PR[0..1] XTAL/ TOSC1 XTAL2/ TOSC2 Oscillator Circuits/ Clock Generation PORT R (2) Real Time Counter Watchdog Oscillator DATA BUS Watchdog Timer ACA Event System Controller PA[0..
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4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.1 Recommended reading  Atmel AVR XMEGA D manual  XMEGA application notes This device data sheet only contains part specific information with a short description of each peripheral and module. The XMEGA D manual describes the modules and peripherals in depth.
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6. AVR CPU 6.1 Features  8/16-bit, high-performance Atmel AVR RISC CPU   137 instructions Hardware multiplier  32x8-bit registers directly connected to the ALU  Stack in RAM  Stack pointer accessible in I/O memory space  Direct addressing of up to 16MB of program memory and 16MB of data memory  True 16/24-bit access to 16/24-bit I/O registers  Efficient support for 8-, 16-, and 32-bit arithmetic  Configuration change protection of system-critical features 6.
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The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation. The ALU is directly connected to the fast-access register file.
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6.5 Program Flow After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The program counter (PC) addresses the next instruction to be fetched. Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
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Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash program memory. 7. Memories 7.
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7.3 Flash Program Memory The Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The flash memory can be accessed for read and write from an external programmer through the PDI or from application software running in the device. All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized in two main sections, the application section and the boot loader section.
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7.3.4 Production Signature Row The production signature row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to the corresponding peripheral registers from software.
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Figure 7-2. Data memory map (hexadecimal address). Byte address ATxmega64D4 0 FFF I/O Registers (4K) 1000 EEPROM (2K) 17FF Byte address ATxmega32D4 0 FFF 1000 13FF RESERVED 2000 2FFF Byte address Internal SRAM (4K) I/O Registers (4K) EEPROM (1K) Byte address ATxmega16D4 0 FFF 1000 13FF RESERVED 2000 2FFF Internal SRAM (4K) I/O Registers (4K) EEPROM (1K) RESERVED 2000 27FF Internal SRAM (2K) ATxmega128D4 0 FFF I/O Registers (4K) 1000 EEPROM (2K) 17FF RESERVED 2000 3FFF 7.
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7.8 Data Memory and Bus Arbitration Since the data memory is organized as four separate sets of memories, the bus masters (CPU, etc.) can access different memory sections at the same time. 7.9 Memory Timing Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from SRAM takes two cycles. EEPROM page load (write) takes one cycle, and three cycles are required for read. For burst read, new data are available every second cycle.
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Table 7-3. Number of Bytes and Pages in the EEPROM.
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8. Event System 8.
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9. System Clock and Clock options 9.1 Features  Fast start-up time  Safe run-time clock switching  Internal oscillators: 32MHz run-time calibrated and tuneable oscillator 2MHz run-time calibrated oscillator  32.768kHz calibrated oscillator  32kHz ultra low power (ULP) oscillator with 1kHz output    External clock options 0.4MHz - 16MHz crystal oscillator 32.
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Figure 9-1. The clock system, clock sources and clock distribution. Real Time Counter Peripherals RAM AVR CPU Non-Volatile Memory clkPER clkCPU clkPER2 clkPER4 Brown-out Detector System Clock Prescalers Watchdog Timer clkSYS clkRTC System Clock Multiplexer (SCLKSEL) RTCSRC DIV32 DIV32 DIV32 PLL PLLSRC DIV4 XOSCSEL 32 kHz Int. ULP 32.768 kHz Int. OSC 32.768 kHz TOSC 32 MHz Int. Osc 2 MHz Int. Osc XTAL2 XTAL1 TOSC2 TOSC1 9.3 0.
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1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device. This oscillator can be selected as the clock source for the RTC. 9.3.2 32.768kHz Calibrated Internal Oscillator This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the oscillator frequency.
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10. Power Management and Sleep Modes 10.1 Features  Power management for adjusting power consumption and functions  Five sleep modes Idle Power down  Power save  Standby  Extended standby    Power reduction register to disable clock and turn off unused peripherals in active and idle modes 10.2 Overview Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.
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10.3.3 Power-save Mode Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt. 10.3.4 Standby Mode Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time. 10.3.
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11. System Control and Reset 11.1 Features  Reset the microcontroller and set it to initial state when a reset source goes active  Multiple reset sources that cover different situations       Power-on reset External reset Watchdog reset Brownout reset PDI reset Software reset  Asynchronous operation  No running system clock in the device is required for reset  Reset status register for reading the reset source from the application code 11.
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11.4 Reset Sources 11.4.1 Power-on Reset A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises and reaches the POR threshold voltage (VPOT), and this will start the reset sequence. The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level. The VPOT level is higher for falling VCC than for rising VCC. Consult the datasheet for POR characteristics data. 11.4.
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12. WDT – Watchdog Timer 12.1 Features  Issues a device reset if the timer is not reset before its timeout period  Asynchronous operation from dedicated oscillator  1kHz output of the 32kHz ultra low power oscillator  11 selectable timeout periods, from 8ms to 8s  Two operation modes:   Normal mode Window mode  Configuration lock to prevent unwanted changes 12.2 Overview The watchdog timer (WDT) is a system function for monitoring correct program operation.
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13. Interrupts and Programmable Multilevel Interrupt Controller 13.
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Table 13-1. Reset and interrupt vectors.
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14. I/O Ports 14.
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14.3 Output Driver All port pins (Pxn) have programmable output configuration. 14.3.1 Push-pull Figure 14-1. I/O configuration - Totem-pole. DIRxn OUTxn Pxn INxn 14.3.2 Pull-down Figure 14-2. I/O configuration - Totem-pole with pull-down (on input). DIRxn OUTxn Pxn INxn 14.3.3 Pull-up Figure 14-3. I/O configuration - Totem-pole with pull-up (on input). DIRxn OUTxn Pxn INxn 14.3.4 Bus-keeper The bus-keeper’s weak output produces the same logical level as the last output level.
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Figure 14-4. I/O configuration - Totem-pole with bus-keeper. DIRxn OUTxn Pxn INxn 14.3.5 Others Figure 14-5. Output configuration - Wired-OR with optional pull-down. OUTxn Pxn INxn Figure 14-6. I/O configuration - Wired-AND with optional pull-up. INxn Pxn OUTxn 14.4 Input sensing Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 14-7.
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Figure 14-7. Input sensing system overview. Asynchronous sensing EDGE DETECT Interrupt Control IRQ Synchronous sensing Pxn Synchronizer INn D Q D R Q EDGE DETECT Synchronous Events R INVERTED I/O Asynchronous Events When a pin is configured with inverted I/O, the pin value is inverted before the input sensing. 14.5 Alternate Port Functions Most port pins have alternate pin functions in addition to being a general purpose I/O pin.
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15. TC0/1 – 16-bit Timer/Counter Type 0 and 1 15.
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Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and highside output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It can also generate a synchronized bit pattern across the port pins.
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16. TC2 Timer/Counter Type 2 16.
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17. AWeX – Advanced Waveform Extension 17.
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18. Hi-Res – High Resolution Extension 18.1 Features  Increases waveform generator resolution up to 8x (three bits)  Supports frequency, single-slope PWM, and dual-slope PWM generation  Supports the AWeX when this is used for the same timer/counter 18.2 Overview The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a timer/counter by four or eight.
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19. RTC – 16-bit Real-Time Counter 19.1 Features  16-bit resolution  Selectable clock source 32.768kHz external crystal External clock  32.768kHz internal oscillator  32kHz internal ULP oscillator    Programmable 10-bit clock prescaling  One compare register  One period register  Clear counter on period overflow  Optional interrupt/event on overflow and compare match 19.
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20. TWI – Two-Wire Interface 20.
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21. SPI – Serial Peripheral Interface 21.1 Features  Two identical SPI peripherals  Full-duplex, three-wire synchronous data transfer  Master or slave operation  Lsb first or msb first data transfer  Eight programmable bit rates  Interrupt flag at the end of transmission  Write collision flag to indicate data collision  Wake up from idle sleep mode  Double speed master mode 21.
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22. USART 22.
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23. IRCOM – IR Communication Module 23.1 Features  Pulse modulation/demodulation for infrared communication  IrDA compatible for baud rates up to 115.2kbps  Selectable pulse modulation scheme 3/16 of the baud rate period Fixed pulse period, 8-bit programmable  Pulse modulation disabled    Built-in filtering  Can be connected to and used by any USART 23.2 Overview Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates up to 115.2Kbps.
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24. CRC – Cyclic Redundancy Check Generator 24.1 Features  Cyclic redundancy check (CRC) generation and checking for Communication data Program or data in flash memory  Data in SRAM and I/O memory space    Integrated with flash memory and CPU   Automatic CRC of the complete or a selectable range of the flash memory CPU can load data to the CRC generator through the I/O interface  CRC polynomial software selectable to   CRC-16 (CRC-CCITT) CRC-32 (IEEE 802.3)  Zero remainder detection 24.
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25. ADC – 12-bit Analog to Digital Converter 25.1 Features  One Analog to Digital Converters (ADC)  12-bit resolution  Up to 200 thousand samples per second   Down to 3.6µs conversion time with 8-bit resolution Down to 5.
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Figure 25-1. ADC overview. Compare Register ADC0 • • • ADC11 < > VINP Internal signals ADC0 • • • ADC7 Threshold (Int Req) CH0 Result VINN Internal 1.00V Internal VCC/1.6V Internal VCC/2 AREFA AREFB Reference Voltage The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 5.0µs for 12-bit to 3.6µs for 8-bit result. ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding.
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26. AC – Analog Comparator 26.
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Figure 26-1. Analog comparator overview. Pin Input + AC0OUT Pin Input Hysteresis Enable Voltage Scaler ACnMUXCTRL ACnCTRL Interrupt Mode WINCTRL Enable Bandgap Interrupt Sensititivity Control & Window Function Interrupts Events Hysteresis + Pin Input AC1OUT Pin Input The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in Figure 26-2. Figure 26-2. Analog comparator window function.
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27. Programming and Debugging 27.
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28. Pinout and Pin Functions The device pinout is shown in ”Pinout/Block Diagram” on page 3. In addition to general purpose I/O functionality, each pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the pin functions can be used at time. 28.1 Alternate Pin Function Description The tables below show the notation for all pin functions available and describe its function. 28.1.
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28.1.6 Oscillators, Clock and Event TOSCn Timer Oscillator pin n XTALn Input/Output for Oscillator pin n CLKOUT Peripheral Clock Output EVOUT Event Channel Output RTCOUT RTC Clock Source Output 28.1.
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28.2 Alternate Pin Functions The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that enable and use the alternate pin functions. For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the first table where this apply. Table 28-1. Port A - alternate functions.
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Table 28-3. Port C - alternate functions. PORT C PIN# INTERRUPT TCC0(1)(2) AWEXC TCC1 USARTC0(3) SPIC(4) TWIC CLOCKOUT GND 8 VCC 9 PC0 10 SYNC OC0A OC0ALS PC1 11 SYNC OC0B OC0AHS XCK0 PC2 12 SYNC/ASYNC OC0C OC0BLS RXD0 PC3 13 SYNC OC0D OC0BHS TXD0 PC4 14 SYNC OC0CLS OC1A SS PC5 15 SYNC OC0CHS OC1B MOSI PC6 16 SYNC OC0DLS MISO clkRTC PC7 17 SYNC OC0DHS SCK clkPER Notes: 1. 2. 3. 4. 5. 6.
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PORT E PIN # INTERRUPT TCE0 VCC 31 PE2 32 SYNC/ASYNC OC0C PE3 33 SYNC OC0D TWIE Table 28-6. Port F - alternate functions. PORT R PIN # INTERRUPT PDI XTAL TOSC(1) PDI 34 PDI_DATA RESET 35 PDI_CLOCK PRO 36 SYNC XTAL2 TOSC2 PR1 37 SYNC XTAL1 TOSC1 Note: 1.
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29. Peripheral Module Address Map The address maps show the base address for each peripheral and module in Atmel AVR XMEGA D4. For complete register description and summary for each peripheral module, refer to the XMEGA D manual. Table 29-1. Peripheral module address map.
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Base address Name Description 0x0680 PORTE Port E 0x07E0 PORTR Port R 0x0800 TCC0 Timer/counter 0 on port C 0x0840 TCC1 Timer/counter 1 on port C 0x0880 AWEXC Advanced waveform extension on port C 0x0890 HIRESC High resolution extension on port C 0x08A0 USARTC0 0x08C0 SPIC 0x08F8 IRCOM 0x0900 TCD0 0x09A0 USARTD0 0x09C0 SPID Serial peripheral interface on port D 0x0A00 TCE0 Timer/counter 0 on port E USART 0 on port C Serial peripheral interface on port C Infrared communic
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30.
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Mnemonics Operands Description RCALL k Relative Call Subroutine Operation Flags #Clocks PC  PC + k + 1 None 2 / 3(1) ICALL Indirect Call to (Z) PC(15:0) PC(21:16)   Z, 0 None 2 / 3(1) EICALL Extended Indirect Call to (Z) PC(15:0) PC(21:16)   Z, EIND None 3(1) call Subroutine PC  k None 3 / 4(1) RET Subroutine Return PC  STACK None 4 / 5(1) RETI Interrupt Return PC  STACK I 4 / 5(1) if (Rd = Rr) PC  PC + 2 or 3 None 1/2/3 CALL k CPSE Rd,Rr Com
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Mnemonics Operands Description LDI Rd, K Load Immediate Operation Rd  Flags K #Clocks None 1 (1)(2) LDS Rd, k Load Direct from data space Rd  (k) None 2 LD Rd, X Load Indirect Rd  (X) None 1(1)(2) LD Rd, X+ Load Indirect and Post-Increment Rd X   (X) X+1 None 1(1)(2) LD Rd, -X Load Indirect and Pre-Decrement X  X - 1, Rd  (X)   X-1 (X) None 2(1)(2) LD Rd, Y Load Indirect Rd  (Y)  (Y) None 1(1)(2) LD Rd, Y+ Load Indirect and Post-Increment Rd
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Mnemonics Operands Description Operation SPM Z+ Store Program Memory and Post-Increment by 2 IN Rd, A In From I/O Location OUT A, Rr Out To I/O Location PUSH Rr Push Register on Stack POP Rd XCH Flags #Clocks (RAMPZ:Z) Z   R1:R0, Z+2 None - Rd  I/O(A) None 1 I/O(A)  Rr None 1 STACK  Rr None 1(1) Pop Register from Stack Rd  STACK None 2(1) Z, Rd Exchange RAM location Temp Rd (Z)    Rd, (Z), Temp None 2 LAS Z, Rd Load and Set RAM location Temp
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Mnemonics Operands Description Operation Flags #Clocks SES Set Signed Test Flag S  1 S 1 CLS Clear Signed Test Flag S  0 S 1 SEV Set Two’s Complement Overflow V  1 V 1 CLV Clear Two’s Complement Overflow V  0 V 1 SET Set T in SREG T  1 T 1 CLT Clear T in SREG T  0 T 1 SEH Set Half Carry Flag in SREG H  1 H 1 CLH Clear Half Carry Flag in SREG H  0 H 1 None 1 None 1 MCU control instructions BREAK Break NOP No Operation SLEEP Sleep
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31. Packaging information 31.1 44A PIN 1 IDENTIFIER PIN 1 e B E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.
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31.2 44M1 D Marked Pin# 1 ID E SEATING PLANE A1 TOP VIEW A3 A K L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle E2 Option B K Option C b e Pin #1 Chamfer (C 0.30) Pin #1 Notch (0.20 R) BOTTOM VIEW COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A3 0.20 REF b 0.18 0.23 0.30 D 6.90 7.00 7.10 D2 5.00 5.20 5.40 E 6.90 7.00 7.10 E2 5.00 5.20 5.40 e Note: JEDEC Standard MO-220, Fig.
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31.3 49C2 E A1 BALL ID 0.10 D A1 TOP VIEW A A2 SIDE VIEW E1 G e F E D D1 COMMON DIMENSIONS (Unit of Measure = mm) C B 1 A1 BALL CORNER MIN NOM MAX A – – 1.00 A1 0.20 – – SYMBOL A 2 3 4 5 b 6 7 e BOTTOM VIEW 49 - Ø0.35 ±0.05 A2 0.65 – – D 4.90 5.00 5.10 D1 E 3.90 BSC 4.90 5.00 E1 b NOTE 5.10 3.90 BSC 0.30 0.35 e 0.40 0.65 BSC 3/14/08 Package Drawing Contact: packagedrawings@atmel.com TITLE 49C2, 49-ball (7 x 7 array), 0.65mm pitch, 5.0 x 5.0 x 1.
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32. Electrical Characteristics All typical values are measured at T = 25C unless other temperature condition is given. All minimum and maximum values are valid across operating temperature and voltage unless other conditions are given. 32.1 ATxmega16D4 32.1.1 Absolute Maximum Ratings Stresses beyond those listed in Table 32-1 under may cause permanent damage to the device.
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The maximum CPU clock frequency depends on VCC. As shown in Figure 32-15 the Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V. Figure 32-1. Maximum Frequency vs. VCC. MHz 32 Safe Operating Area 12 1.6 1.8 2.7 3.
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32.1.3 Current consumption Table 32-4. Current consumption for Active mode and sleep modes. Symbol Parameter Condition 32kHz, Ext. Clk Active power consumption(1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32MHz, Ext. Clk 32kHz, Ext. Clk Idle power consumption(1) 1MHz, Ext. Clk 2MHz, Ext. Clk ICC 32MHz, Ext. Clk T = 25°C T = 85°C Power-down power consumption WDT and sampled BOD enabled, T = 25°C WDT and sampled BOD enabled, T = 85°C Power-save power consumption(2) Reset power consumption Notes: 1. 2. Min.
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Table 32-5. Current consumption for modules and peripherals. Symbol Parameter Condition(1) Min. ULP oscillator 0.8 32.768kHz int. oscillator 29 2MHz int. oscillator 32MHz int. oscillator PLL BOD Max. Units 85 DFLL enabled with 32.768kHz int. osc. as reference 115 245 DFLL enabled with 32.768kHz int. osc. as reference 410 20x multiplication factor, 32MHz int. osc. DIV4 as reference 290 Watchdog timer ICC Typ. µA 1.0 Continuous mode 138 Sampled mode, includes ULP oscillator 1.
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32.1.4 Wake-up time from sleep modes Table 32-6. Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Wake-up time from idle, standby, and extended standby mode twakeup Wake-up time from power-save and power-down mode Note: 1. Condition Min. Typ.(1) External 2MHz clock 2.0 32.768kHz internal oscillator 120 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 External 2MHz clock 5.0 32.768kHz internal oscillator 320 2MHz internal oscillator 9.
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32.1.5 I/O Pin Characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 32-7. I/O pin characteristics. Symbol (1) IOH / IOL (2) Parameter Max. Units -20 20 mA VCC = 2.4 - 3.6V 0.7*Vcc VCC+0.5 VCC = 1.6 - 2.4V 0.8*VCC VCC+0.5 VCC = 2.4- 3.6V -0.5 0.3*VCC VCC = 1.6 - 2.4V -0.5 0.
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32.1.6 ADC characteristics Table 32-8. Power supply, reference and input range. Symbol Parameter AVCC Analog supply voltage VREF Reference voltage Condition Min. Typ. Max. VCC- 0.3 VCC+ 0.3 1 AVCC- 0.6 Units V Rin Input resistance Switched 4.
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Table 32-10. Accuracy characteristics. Symbol RES Condition(2) Parameter Resolution 12-bit resolution Differential mode INL(1) Integral non-linearity Differential mode Differential non-linearity Single ended unsigned mode Offset Error Typ. Max. Differential 8 12 12 Single ended signed 7 11 11 Single ended unsigned 8 12 12 16ksps, VREF = 3V 0.5 1 16ksps, all VREF 0.8 2 200ksps, VREF = 3V 0.6 1 1 2 16ksps, VREF = 3.0V 0.5 1 16ksps, all VREF 1.3 2 16ksps, VREF = 3V 0.
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Table 32-11. Gain stage characteristics. Rin Input resistance Switched in normal mode 4.0 k Csample Input capacitance Switched in normal mode 4.4 pF Signal range Gain stage output Propagation delay ADC conversion rate 1/2 Clock frequency Same as ADC 100 Gain Error Offset Error, input referred 0 1 0.5x gain, normal mode -1 1x gain, normal mode -1 8x gain, normal mode -1 64x gain, normal mode 10 0.
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32.1.8 Bandgap and Internal 1.0V Reference Characteristics Table 32-13. Bandgap and Internal 1.0V reference characteristics. Symbol Parameter Startup time Condition Min. As reference for ADC Typ. 1 ClkPER + 2.5µs As input voltage to ADC and AC 1.1 Internal 1.00V reference T= 85°C, after calibration Variation over voltage and temperature Calibrated at T= 85°C, VCC = 3.0V 0.98 1 Units µs 1.5 Bandgap voltage INT1V Max. 1.02 ±1.0 V % 32.1.9 Brownout Detection Characteristics Table 32-14.
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32.1.11 Power-on Reset Characteristics Table 32-16. Power-on reset characteristics. Symbol Parameter VPOT- (1) POR threshold voltage falling VCC VPOT+ POR threshold voltage rising VCC Note: 1. Condition Min. Typ. VCC falls faster than 1V/ms 0.4 1.0 VCC falls at 1V/ms or slower 0.8 1.0 1.3 Max. Units V 1.59 VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+. 32.1.12 Flash and EEPROM Memory Characteristics Table 32-17. Endurance and data retention.
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32.1.13 Clock and Oscillator Characteristics 32.1.13.1 Calibrated 32.768kHz Internal Oscillator characteristics Table 32-19. 32.768kHz internal oscillator characteristics. Symbol Parameter Condition Min. Frequency Factory calibration accuracy Typ. Max. 32.768 T = 85C, VCC = 3.0V User calibration accuracy Units kHz -0.5 0.5 -0.5 0.5 % 32.1.13.2 Calibrated 2MHz RC Internal Oscillator characteristics Table 32-20. 2MHz internal oscillator characteristics.
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32.1.13.5 Internal Phase Locked Loop (PLL) characteristics Table 32-23. Internal PLL characteristics. Symbol fIN Input frequency Output frequency (1) fOUT Note: Parameter 1. Condition Min. Typ. Output frequency must be within fOUT 0.4 64 VCC= 1.6 - 1.8V 20 48 VCC= 2.7 - 3.6V 20 128 Start-up time 25 Re-lock time 25 Max. Units MHz µs The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency. 32.
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32.1.13.7 External 16MHz crystal oscillator and XOSC characteristics Table 32-25. External 16MHz crystal oscillator and XOSC characteristics. . Symbol Parameter Cycle to cycle jitter Condition XOSCPWR=0 Min. FRQRANGE=0 0 FRQRANGE=1, 2, or 3 0 XOSCPWR=1 Long term jitter XOSCPWR=0 XOSCPWR=0 FRQRANGE=0 0 FRQRANGE=1, 2, or 3 0 XOSCPWR=0 FRQRANGE=0 0.03 FRQRANGE=1 0.03 FRQRANGE=2 or 3 0.
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Symbol Parameter Condition Min. 9MHz crystal 1500 12MHz crystal 650 16MHz crystal 270 XOSCPWR=1, FRQRANGE=2, CL=20pF 12MHz crystal 1000 16MHz crystal 440 XOSCPWR=1, FRQRANGE=3, CL=20pF 12MHz crystal 1300 16MHz crystal 590 XOSCPWR=1, FRQRANGE=1, CL=20pF Negative impedance RQ ESR Start-up time Typ. SF = safety factor Max.  min(RQ)/SF XOSCPWR=0, FRQRANGE=0 0.4MHz resonator, CL=100pF 1.0 XOSCPWR=0, FRQRANGE=1 2MHz crystal, CL=20pF 2.
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Figure 32-4. TOSC input capacitance. CL1 CL2 Device internal External TOSC1 TOSC2 32.768kHz crystal The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without external capacitors. 32.1.14 SPI Characteristics Figure 32-5. SPI timing requirements in master mode.
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Figure 32-6. SPI timing requirements in slave mode.
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Table 32-27. SPI timing characteristics and requirements. Symbol Parameter Condition Min. Typ. Max. tSCK SCK period Master (See Table 20-3 in XMEGA C Manual) tSCKW SCK high/low width Master 0.5*SCK tSCKR SCK rise time Master 2.7 tSCKF SCK fall time Master 2.7 tMIS MISO setup to SCK Master 10 tMIH MISO hold after SCK Master 10 tMOS MOSI setup SCK Master 0.
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Table 32-28. Two-wire interface characteristics. Symbol Parameter Condition Min. Typ. Max. VIH Input high voltage 0.7VCC VCC+0.5 VIL Input low voltage -0.5 0.3VCC Vhys Hysteresis of Schmitt trigger inputs VOL Output low voltage tr Rise time for both SDA and SCL tof Output fall time from VIHmin to VILmax tSP Spikes suppressed by input filter II Input current for each I/O Pin CI Capacitance for each I/O Pin fSCL SCL clock frequency 0.
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32.2 ATxmega32D4 32.2.1 Absolute Maximum Ratings Stresses beyond those listed in Table 32-29 under may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 32-29. Absolute maximum ratings. Symbol Parameter Condition Min. Typ. -0.
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Figure 32-8. Maximum Frequency vs. VCC. MHz 32 Safe Operating Area 12 1.6 1.8 2.7 3.
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32.2.3 Current consumption Table 32-32. Current consumption for Active mode and sleep modes. Symbol Parameter Condition 32kHz, Ext. Clk Active power consumption(1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32MHz, Ext. Clk 32kHz, Ext. Clk Idle power consumption(1) 1MHz, Ext. Clk 2MHz, Ext. Clk ICC 32MHz, Ext. Clk T = 25°C T = 85°C Power-down power consumption WDT and sampled BOD enabled, T = 25°C WDT and sampled BOD enabled, T = 85°C Power-save power consumption(2) Reset power consumption Notes: 1. 2. Min.
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Table 32-33. Current consumption for modules and peripherals. Symbol Parameter Condition(1) Min. ULP oscillator 0.8 32.768kHz int. oscillator 29 2MHz int. oscillator 32MHz int. oscillator PLL BOD Max. Units 85 DFLL enabled with 32.768kHz int. osc. as reference 115 245 DFLL enabled with 32.768kHz int. osc. as reference 410 20x multiplication factor, 32MHz int. osc. DIV4 as reference 290 Watchdog timer ICC Typ. µA 1.0 Continuous mode 138 Sampled mode, includes ULP oscillator 1.
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32.2.4 Wake-up time from sleep modes Table 32-34. Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Wake-up time from idle, standby, and extended standby mode twakeup Wake-up time from power-save and power-down mode Note: 1. Condition Min. Typ. (1) External 2MHz clock 2.0 32.768kHz internal oscillator 120 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 External 2MHz clock 5.0 32.768kHz internal oscillator 320 2MHz internal oscillator 9.
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32.2.5 I/O Pin Characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 32-35. I/O pin characteristics. Symbol (1) IOH / IOL (2) Parameter Max. Units -20 20 mA VCC = 2.4 - 3.6V 0.7*Vcc VCC+0.5 VCC = 1.6 - 2.4V 0.8*VCC VCC+0.5 VCC = 2.4- 3.6V -0.5 0.3*VCC VCC = 1.6 - 2.4V -0.5 0.
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32.2.6 ADC characteristics Table 32-36. Power supply, reference and input range. Symbol Parameter AVCC Analog supply voltage VREF Reference voltage Condition Min. Typ. Max. VCC- 0.3 VCC+ 0.3 1 AVCC- 0.6 Units V Rin Input resistance Switched 4.
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Table 32-38. Accuracy characteristics. Symbol RES Condition(2) Parameter Resolution 12-bit resolution Differential mode INL(1) Integral non-linearity Differential mode Differential non-linearity Single ended unsigned mode Offset Error Gain Error Gain Error Typ. Max. Differential 8 12 12 Single ended signed 7 11 11 Single ended unsigned 8 12 12 16ksps, VREF = 3V 0.5 1 16ksps, all VREF 0.8 2 200ksps, VREF = 3V 0.6 1 1 2 16ksps, VREF = 3.0V 0.5 1 16ksps, all VREF 1.
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Table 32-39. Gain stage characteristics. Rin Input resistance Switched in normal mode 4.0 k Csample Input capacitance Switched in normal mode 4.4 pF Signal range Gain stage output Propagation delay ADC conversion rate 1/2 Clock rate Same as ADC 100 Gain error Offset error, input referred 0 1 0.5x gain, normal mode -1 1x gain, normal mode -1 8x gain, normal mode -1 64x gain, normal mode 10 0.
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32.2.8 Bandgap and Internal 1.0V Reference Characteristics Table 32-41. Bandgap and Internal 1.0V reference characteristics. Symbol Parameter Startup time Condition Min. As reference for ADC Typ. 1 ClkPER + 2.5µs As input voltage to ADC and AC 1.1 Internal 1.00V reference T= 85°C, after calibration Variation over voltage and temperature Calibrated at T= 85°C, VCC = 3.0V 0.98 1 Units µs 1.5 Bandgap voltage INT1V Max. 1.02 ±1.0 V % 32.2.9 Brownout Detection Characteristics Table 32-42.
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32.2.11 Power-on Reset Characteristics Table 32-44. Power-on reset characteristics. Symbol Parameter VPOT- (1) POR threshold voltage falling VCC VPOT+ POR threshold voltage rising VCC Note: 1. Condition Min. Typ. VCC falls faster than 1V/ms 0.4 1.0 VCC falls at 1V/ms or slower 0.8 1.0 Max. Units V 1.3 1.59 Typ. Max. VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+. 32.2.12 Flash and EEPROM Memory Characteristics Table 32-45.
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32.2.13 Clock and Oscillator Characteristics 32.2.13.1 Calibrated 32.768kHz Internal Oscillator characteristics Table 32-47. 32.768kHz internal oscillator characteristics. Symbol Parameter Condition Min. Frequency Factory calibration accuracy Typ. Max. 32.768 T = 85C, VCC = 3.0V User calibration accuracy Units kHz -0.5 0.5 -0.5 0.5 % 32.2.13.2 Calibrated 2MHz RC Internal Oscillator characteristics Table 32-48. 2MHz internal oscillator characteristics.
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32.2.13.5 Internal Phase Locked Loop (PLL) characteristics Table 32-51. Internal PLL characteristics. Symbol fIN Input frequency Output frequency(1) fOUT Note: Parameter 1. Condition Min. Typ. Output frequency must be within fOUT 0.4 64 VCC= 1.6 - 1.8V 20 48 VCC= 2.7 - 3.6V 20 128 Start-up time 25 Re-lock time 25 Max. Units MHz µs The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency. 32.
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32.2.13.7 External 16MHz crystal oscillator and XOSC characteristics Table 32-53. External 16MHz crystal oscillator and XOSC characteristics. . Symbol Parameter Cycle to cycle jitter Condition XOSCPWR=0 Min. FRQRANGE=0 0 FRQRANGE=1, 2, or 3 0 XOSCPWR=1 Long term jitter XOSCPWR=0 XOSCPWR=0 FRQRANGE=0 0 FRQRANGE=1, 2, or 3 0 XOSCPWR=0 FRQRANGE=0 0.03 FRQRANGE=1 0.03 FRQRANGE=2 or 3 0.
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Symbol Parameter Condition Negative impedance ESR Start-up time Typ. 9MHz crystal 390 12MHz crystal 50 16MHz crystal 10 9MHz crystal 1500 12MHz crystal 650 16MHz crystal 270 XOSCPWR=1, FRQRANGE=2, CL=20pF 12MHz crystal 1000 16MHz crystal 440 XOSCPWR=1, FRQRANGE=3, CL=20pF 12MHz crystal 1300 16MHz crystal 590 XOSCPWR=1, FRQRANGE=0, CL=20pF RQ Min. XOSCPWR=1, FRQRANGE=1, CL=20pF SF = safety factor Max.  min(RQ)/SF XOSCPWR=0, FRQRANGE=0 0.4MHz resonator, CL=100pF 1.
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32.2.13.8 External 32.768kHz crystal oscillator and TOSC characteristics Table 32-54. External 32.768kHz crystal oscillator and TOSC characteristics. Symbol Parameter Condition ESR/R1 Recommended crystal equivalent series resistance (ESR) Typ. Max. Crystal load capacitance 6.5pF 60 Crystal load capacitance 9.0pF 35 Crystal load capacitance 12pF 28 CTOSC1 Parasitic capacitance TOSC1 pin 3.5 CTOSC2 Parasitic capacitance TOSC2 pin 3.5 Recommended safety factor Note: Min.
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32.2.14 SPI Characteristics Figure 32-12.SPI timing requirements in master mode. SS tSCKR tMOS tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data Input) tMIH tSCK MSB LSB tMOH tMOH MOSI (Data Output) MSB LSB Figure 32-13.SPI timing requirements in slave mode.
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Table 32-55. SPI timing characteristics and requirements. Symbol Parameter Condition Min. Typ. Max. tSCK SCK period Master (See Table 20-3 in XMEGA C Manual) tSCKW SCK high/low width Master 0.5*SCK tSCKR SCK rise time Master 2.7 tSCKF SCK fall time Master 2.7 tMIS MISO setup to SCK Master 10 tMIH MISO hold after SCK Master 10 tMOS MOSI setup SCK Master 0.
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Table 32-56. Two-wire interface characteristics. Symbol Parameter Condition Min. Typ. Max. VIH Input high voltage 0.7VCC VCC+0.5 VIL Input low voltage -0.5 0.3VCC Vhys Hysteresis of Schmitt trigger inputs VOL Output low voltage tr Rise time for both SDA and SCL tof Output fall time from VIHmin to VILmax tSP Spikes suppressed by input filter II Input current for each I/O Pin CI Capacitance for each I/O Pin fSCL SCL clock frequency 0.
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32.3 ATxmega64D4 32.3.1 Absolute Maximum Ratings Stresses beyond those listed in Table 32-57 under may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 32-57. Absolute maximum ratings. Symbol Parameter Condition Min. Typ. -0.
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The maximum CPU clock frequency depends on VCC. As shown in Figure 32-15 the Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V. Figure 32-15.Maximum Frequency vs. VCC. MHz 32 Safe Operating Area 12 1.6 1.8 2.7 3.
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32.3.3 Current consumption Table 32-60. Current consumption for active mode and sleep modes. Symbol Parameter Condition 32kHz, Ext. Clk Active power consumption(1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32MHz, Ext. Clk 32kHz, Ext. Clk Idle power consumption(1) 1MHz, Ext. Clk 2MHz, Ext. Clk ICC 32MHz, Ext. Clk T = 25°C T = 85°C Power-down power consumption WDT and sampled BOD enabled, T = 25°C WDT and sampled BOD enabled, T = 85°C Power-save power consumption(2) Reset power consumption Notes: 1. 2. Min.
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Table 32-61. Current consumption for modules and peripherals. Symbol Parameter Condition(1) Min. Typ. ULP oscillator 1.0 32.768kHz int. oscillator 27 2MHz int. oscillator 32MHz int. oscillator PLL ICC Units 85 DFLL enabled with 32.768kHz int. osc. as reference 115 270 DFLL enabled with 32.768kHz int. osc. as reference 460 20x multiplication factor, 32MHz int. osc. DIV4 as reference 220 Watchdog Timer BOD Max. µA 1.0 Continuous mode 138 Sampled mode, includes ULP oscillator 1.
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32.3.4 Wake-up time from sleep modes Table 32-62. Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Wake-up time from Idle, Standby, and Extended Standby mode twakeup Wake-up time from Power-save and Power-down mode Note: 1. Condition Min. Typ.(1) External 2MHz clock 2.0 32.768kHz internal oscillator 120 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 External 2MHz clock 4.5 32.768kHz internal oscillator 320 2MHz internal oscillator 9.
PAGE 106
32.3.5 I/O Pin Characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 32-63. I/O pin characteristics. Symbol (1) IOH / IOL(2) Parameter Max. Units -15 15 mA VCC = 2.7 - 3.6V 2 VCC+0.3 V VCC = 2.0 - 2.7V 0.7*VCC VCC+0.3 VCC = 1.6 - 2.0V 0.7*VCC VCC+0.3 VCC = 2.7- 3.6V -0.3 0.3*VCC VCC = 2.0 - 2.7V -0.3 0.3*VCC VCC = 1.6 - 2.0V -0.3 0.
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32.3.6 ADC characteristics Table 32-64. Power supply, reference and input range. Symbol Parameter AVCC Analog supply voltage VREF Reference voltage Condition Min. Typ. Max. VCC- 0.3 VCC+ 0.3 1.0 AVCC- 0.6 Units V Rin Input resistance Switched 4.0 k Csample Input capacitance Switched 4.4 pF RAREF Reference input resistance (leakage only) >10 M CAREF Reference input capacitance Static load 7.
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Table 32-66. Accuracy characteristics. Symbol Parameter Condition(2) RES Resolution Programmable to 8 or 12 bit Min. Typ. Max. Units 8 12 12 Bits VCC-1.0V < VREF< VCC-0.6V ±1.2 ±3 All VREF ±1.5 ±4 VCC-1.0V < VREF< VCC-0.6V ±1.0 ±3 All VREF ±1.5 ±4 guaranteed monotonic <±0.8 <±1 50ksps INL(1) Integral non-linearity 200ksps DNL (1) Differential non-linearity Offset error -1 mV Temperature drift <0.01 mV/K Operating voltage drift <0.
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Table 32-67. Gain stage characteristics. Symbol Parameter Condition Min. Typ. Max. Units Rin Input resistance Switched in normal mode 4.0 k Csample Input capacitance Switched in normal mode 4.4 pF Signal range Gain stage output Propagation delay ADC conversion rate Sample rate Same as ADC INL(1) Integral non-linearity Gain error Offset error, input referred 0 14 50ksps All gain settings ±1.5 1x gain, normal mode -0.8 8x gain, normal mode -2.5 64x gain, normal mode -3.
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32.3.8 Bandgap and Internal 1.0V Reference Characteristics Table 32-69. Bandgap and Internal 1.0V reference characteristics. Symbol Parameter Startup time Condition Min. As reference for ADC Max. 1 ClkPER + 2.5µs As input voltage to ADC and AC 1.1 Internal 1.00V reference T= 85°C, after calibration Variation over voltage and temperature Relative to T= 85°C, VCC = 3.0V 0.99 1.0 Units µs 1.5 Bandgap voltage INT1V Typ. 1.01 ±1.5 V % 32.3.9 Brownout Detection Characteristics Table 32-70.
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32.3.10 External Reset Characteristics Table 32-71. External reset characteristics. Symbol tEXT Parameter Condition Minimum reset pulse width Reset threshold voltage (VIH) VRST Reset threshold voltage (VIL) RRST Min. Typ. 1000 95 VCC = 2.7 - 3.6V 0.60*VCC VCC = 1.6 - 2.7V 0.60*VCC Max. ns 0.50*VCC VCC = 2.7 - 3.6V 0.40*VCC VCC = 1.6 - 2.7V 0.50*VCC Reset pin pull-up resistor Units 25 V k 32.3.11 Power-on Reset Characteristics Table 32-72. Power-on reset characteristics.
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Table 32-74. Programming time. Symbol Parameter Chip erase Flash EEPROM Notes: 1. 2. Condition Min. Typ.(1) 64KB Flash, EEPROM(2) and SRAM erase 55 Page erase 4 Page write 4 Atomic Page Erase and write 8 Page erase 4 Page write 4 Atomic Page erase and write 8 Max. Units ms Programming is timed from the 2MHz internal oscillator. EEPROM is not erased if the EESAVE fuse is programmed. 32.3.13 Clock and Oscillator Characteristics 32.3.13.1 Calibrated 32.
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32.3.13.3 Calibrated and tunable 32MHz internal oscillator characteristics Table 32-77. 32MHz internal oscillator characteristics. Symbol Parameter Frequency range Condition Min. DFLL can tune to this frequency over voltage and temperature 30 Factory calibrated frequency Factory calibration accuracy Typ. Max. 55 Units MHz 32 T = 85C, VCC= 3.0V User calibration accuracy -1.5 1.5 -0.2 0.2 % Max. Units DFLL calibration step size 0.22 32.3.13.
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32.3.13.6 External clock characteristics Figure 32-17.External clock drive waveform tCH tCH tCF tCR VIH1 VIL1 tCL tCK Table 32-80. External clock used as system clock without prescaling. Symbol Clock frequency(1) 1/tCK tCK Clock period tCH Clock high time tCL Clock low time tCR Rise time (for maximum frequency) tCF Fall time (for maximum frequency) tCK Note: Parameter Condition Typ. Max. VCC = 1.6 - 1.8V 0 12 VCC = 2.7 - 3.6V 0 32 VCC = 1.6 - 1.8V 83.3 VCC = 2.7 - 3.6V 31.
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Table 32-81. External clock with prescaler(1) for system clock. Symbo l Parameter Condition Clock frequency(2) 1/tCK tCK Clock period tCH Clock high time Min. Typ. Max. VCC = 1.6 - 1.8V 0 90 VCC = 2.7 - 3.6V 0 142 VCC = 1.6 - 1.8V 11 VCC = 2.7 - 3.6V 7 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 Clock low time tCR Rise time (for maximum frequency) 1.5 tCF Fall time (for maximum frequency) 1.
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Symbol Parameter Condition 0.4MHz resonator, CL=100pF 2.4k 1MHz crystal, CL=20pF 8.7k 2MHz crystal, CL=20pF 2.1k 2MHz crystal 4.
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Symbol Parameter CXTAL1 Parasitic capacitance XTAL1 pin 5.9 CXTAL2 Parasitic capacitance XTAL2 pin 8.3 CLOAD Parasitic capacitance load 3.5 Note: 1. Condition Min. Typ. Max. Units pF Numbers for negative impedance are not tested in production but guaranteed from design and characterization. 32.3.13.8 External 32.768kHz crystal oscillator and TOSC characteristics Table 32-83. External 32.768kHz crystal oscillator and TOSC characteristics.
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32.3.14 SPI Characteristics Figure 32-19.SPI timing requirements in master mode. SS tSCKR tMOS tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data Input) tMIH tSCK MSB LSB tMOH tMOH MOSI (Data Output) MSB LSB Figure 32-20.SPI timing requirements in slave mode.
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Table 32-84. SPI timing characteristics and requirements. Symbol Parameter Condition Min. Typ. Max. tSCK SCK period Master (See Table 17-4 in XMEGA D Manual) tSCKW SCK high/low width Master 0.5*SCK tSCKR SCK rise time Master 2.7 tSCKF SCK fall time Master 2.7 tMIS MISO setup to SCK Master 10 tMIH MISO hold after SCK Master 10 tMOS MOSI setup SCK Master 0.
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32.3.15 Two-Wire Interface Characteristics Table 32-85 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 3221. Figure 32-21.Two-wire Interface bus timing. tof tHIGH tLOW tr SCL tSU;STA tHD;DAT tSU;STO tSU;DAT tHD;STA SDA tBUF Table 32-85. Two-wire interface characteristics. Symbol Parameter Condition Min. Typ. Max.
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Symbol tHD;STA Parameter Hold time (repeated) START condition tLOW Low period of SCL clock tHIGH High period of SCL clock tSU;STA Set-up time for a repeated START condition tHD;DAT Data hold time tSU;DAT Data setup time tSU;STO Setup time for STOP condition Bus free time between a STOP and START condition tBUF Notes: 1. 2. 3. Condition Min. Typ. Max. fSCL  100kHz 4.0 fSCL > 100kHz 0.6 fSCL  100kHz 4.7 fSCL > 100kHz 1.3 fSCL  100kHz 4.0 fSCL > 100kHz 0.6 fSCL  100kHz 4.
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32.4 ATxmega128D4 32.4.1 Absolute Maximum Ratings Stresses beyond those listed in Table 32-86 under may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 32-86. Absolute maximum ratings. Symbol Parameter Condition Min. Typ.
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The maximum CPU clock frequency depends on VCC. As shown in Figure 32-22 the Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V. Figure 32-22.Maximum Frequency vs. VCC. MHz 32 Safe Operating Area 12 1.6 1.8 2.7 3.
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32.4.3 Current consumption Table 32-89. Current consumption for active mode and sleep modes. Symbol Parameter Condition 32kHz, Ext. Clk Active power consumption(1) 1MHz, Ext. Clk 2MHz, Ext. Clk 32MHz, Ext. Clk 32kHz, Ext. Clk Idle power consumption(1) 1MHz, Ext. Clk 2MHz, Ext. Clk ICC 32MHz, Ext. Clk T = 25°C T = 85°C Power-down power consumption WDT and sampled BOD enabled, T = 25°C WDT and sampled BOD enabled, T = 85°C Power-save power consumption(2) Reset power consumption Notes: 1. 2. Min.
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Table 32-90. Current consumption for modules and peripherals. Symbol Parameter Condition(1) Min. Typ. ULP oscillator 1.0 32.768kHz int. oscillator 27 2MHz int. oscillator 32MHz int. oscillator PLL ICC Units 85 DFLL enabled with 32.768kHz int. osc. as reference 115 270 DFLL enabled with 32.768kHz int. osc. as reference 460 20x multiplication factor, 32MHz int. osc. DIV4 as reference 220 Watchdog Timer BOD Max. µA 1.0 Continuous mode 138 Sampled mode, includes ULP oscillator 1.
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32.4.4 Wake-up time from sleep modes Table 32-91. Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Wake-up time from Idle, Standby, and Extended Standby mode twakeup Wake-up time from Power-save and Power-down mode Note: 1. Condition Min. Typ.(1) External 2MHz clock 2.0 32.768kHz internal oscillator 120 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 External 2MHz clock 4.5 32.768kHz internal oscillator 320 2MHz internal oscillator 9.
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32.4.5 I/O Pin Characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 32-92. I/O pin characteristics. Symbol (1) IOH / IOL(2) Parameter Max. Units -15 15 mA VCC = 2.7 - 3.6V 2 VCC+0.3 V VCC = 2.0 - 2.7V 0.7*VCC VCC+0.3 VCC = 1.6 - 2.0V 0.7*VCC VCC+0.3 VCC = 2.7- 3.6V -0.3 0.3*VCC VCC = 2.0 - 2.7V -0.3 0.3*VCC VCC = 1.6 - 2.0V -0.3 0.
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32.4.6 ADC characteristics Table 32-93. Power supply, reference and input range. Symbol Parameter AVCC Analog supply voltage VREF Reference voltage Rin Condition Min. Typ. Max. VCC- 0.3 VCC+ 0.3 1.0 AVCC- 0.6 Units V Input resistance Switched 4.0 k Csample Input capacitance Switched 4.4 pF RAREF Reference input resistance (leakage only) >10 M CAREF Reference input capacitance Static load 7.
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Table 32-95. Accuracy characteristics. Symbol Parameter Condition(2) RES Resolution Programmable to 8 or 12 bit Min. Typ. Max. Units 8 12 12 Bits VCC-1.0V < VREF< VCC-0.6V ±1.2 ±3 All VREF ±1.5 ±4 VCC-1.0V < VREF< VCC-0.6V ±1.0 ±3 All VREF ±1.5 ±4 guaranteed monotonic <±0.8 <±1 50ksps INL(1) Integral non-linearity 200ksps DNL (1) Differential non-linearity Offset error -1 mV Temperature drift <0.01 mV/K Operating voltage drift <0.
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Table 32-96. Gain stage characteristics. Symbol Rin Csample INL(1) Parameter Condition Min. Units Switched in normal mode 4.0 k Input capacitance Switched in normal mode 4.4 pF Signal range Gain stage output Propagation delay ADC conversion rate Sample rate Same as ADC Integral non-linearity Offset error, input referred 0 Noise VCC- 0.6 14 50ksps All gain settings ±1.5 1x gain, normal mode -0.8 8x gain, normal mode -2.5 64x gain, normal mode -3.
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32.4.8 Bandgap and Internal 1.0V Reference Characteristics Table 32-98. Bandgap and Internal 1.0V reference characteristics. Symbol Parameter Startup time Condition Min. As reference for ADC Max. 1 ClkPER + 2.5µs As input voltage to ADC and AC 1.1 Internal 1.00V reference T= 85°C, after calibration Variation over voltage and temperature Relative to T= 85°C, VCC = 3.0V 0.99 1.0 Units µs 1.5 Bandgap voltage INT1V Typ. 1.01 ±1.5 V % 32.4.9 Brownout Detection Characteristics Table 32-99.
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32.4.10 External Reset Characteristics Table 32-100.External reset characteristics. Symbol tEXT Parameter Condition Minimum reset pulse width Reset threshold voltage (VIH) VRST Reset threshold voltage (VIL) RRST Min. Typ. 1000 95 VCC = 2.7 - 3.6V 0.60*VCC VCC = 1.6 - 2.7V 0.60*VCC Max. ns 0.50*VCC VCC = 2.7 - 3.6V 0.40*VCC VCC = 1.6 - 2.7V 0.50*VCC Reset pin pull-up resistor Units 25 V k 32.4.11 Power-on Reset Characteristics Table 32-101.Power-on reset characteristics.
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Table 32-103.Programming time. Symbol Parameter Chip erase Flash EEPROM Notes: 1. 2. Condition Min. Typ.(1) 64KB Flash, EEPROM(2) and SRAM erase 55 Page erase 4 Page write 4 Atomic Page Erase and write 8 Page erase 4 Page write 4 Atomic Page erase and write 8 Max. Units ms Programming is timed from the 2MHz internal oscillator. EEPROM is not erased if the EESAVE fuse is programmed. 32.4.13 Clock and Oscillator Characteristics 32.4.13.1 Calibrated 32.
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32.4.13.3 Calibrated and tunable 32MHz internal oscillator characteristics Table 32-106. 32MHz internal oscillator characteristics. Symbol Parameter Frequency range Condition Min. DFLL can tune to this frequency over voltage and temperature 30 Factory calibrated frequency Factory calibration accuracy Typ. Max. 55 Units MHz 32 T = 85C, VCC= 3.0V User calibration accuracy -1.5 1.5 -0.2 0.2 % Max. Units DFLL calibration step size 0.22 32.4.13.
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32.4.13.6 External clock characteristics Figure 32-24.External clock drive waveform tCH tCH tCF tCR VIH1 VIL1 tCL tCK Table 32-109. External clock used as system clock without prescaling. Symbol Clock frequency(1) 1/tCK tCK Clock period tCH Clock high time tCL Clock low time tCR Rise time (for maximum frequency) tCF Fall time (for maximum frequency) tCK Note: Parameter Condition Typ. Max. VCC = 1.6 - 1.8V 0 12 VCC = 2.7 - 3.6V 0 32 VCC = 1.6 - 1.8V 83.3 VCC = 2.7 - 3.6V 31.
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Table 32-110. External clock with prescaler(1) for system clock. Symbol Parameter Condition Clock frequency(2) 1/tCK tCK Clock period tCH Clock high time Min. Typ. Max. VCC = 1.6 - 1.8V 0 90 VCC = 2.7 - 3.6V 0 142 VCC = 1.6 - 1.8V 11 VCC = 2.7 - 3.6V 7 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 Clock low time tCR Rise time (for maximum frequency) 1.5 tCF Fall time (for maximum frequency) 1.
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Symbol Parameter Condition 0.4MHz resonator, CL=100pF 2.4k 1MHz crystal, CL=20pF 8.7k 2MHz crystal, CL=20pF 2.1k 2MHz crystal 4.
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Symbol Parameter CXTAL1 Parasitic capacitance XTAL1 pin 5.9 CXTAL2 Parasitic capacitance XTAL2 pin 8.3 CLOAD Parasitic capacitance load 3.5 Note: 1. Condition Min. Typ. Max. Units pF Numbers for negative impedance are not tested in production but guaranteed from design and characterization. 32.4.13.8 External 32.768kHz crystal oscillator and TOSC characteristics Table 32-112. External 32.768kHz crystal oscillator and TOSC characteristics.
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32.4.14 SPI Characteristics Figure 32-26.SPI timing requirements in master mode. SS tSCKR tMOS tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data Input) tMIH tSCK MSB LSB tMOH tMOH MOSI (Data Output) MSB LSB Figure 32-27.SPI timing requirements in slave mode.
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Table 32-113. SPI timing characteristics and requirements. Symbol Parameter Condition Min. Typ. Max. tSCK SCK period Master (See Table 17-4 in XMEGA D Manual) tSCKW SCK high/low width Master 0.5*SCK tSCKR SCK rise time Master 2.7 tSCKF SCK fall time Master 2.7 tMIS MISO setup to SCK Master 10 tMIH MISO hold after SCK Master 10 tMOS MOSI setup SCK Master 0.
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32.4.15 Two-Wire Interface Characteristics Table 32-114 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 3228. Figure 32-28.Two-wire Interface bus timing. tof tHIGH tLOW tr SCL tSU;STA tHD;DAT tSU;STO tSU;DAT tHD;STA SDA tBUF Table 32-114. Two-wire interface characteristics. Symbol Parameter Condition Min. Typ. Max.
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Symbol tHD;STA Parameter Hold time (repeated) START condition tLOW Low period of SCL clock tHIGH High period of SCL clock tSU;STA Set-up time for a repeated START condition tHD;DAT Data hold time tSU;DAT Data setup time tSU;STO Setup time for STOP condition Bus free time between a STOP and START condition tBUF Notes: 1. 2. 3. Condition Min. Typ. Max. fSCL  100kHz 4.0 fSCL > 100kHz 0.6 fSCL  100kHz 4.7 fSCL > 100kHz 1.3 fSCL  100kHz 4.0 fSCL > 100kHz 0.6 fSCL  100kHz 4.
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33. Typical Characteristics 33.1 ATxmega16D4 33.1.1 Current consumption 33.1.1.1 Active mode supply current Figure 33-1. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 600 550 3.6V 500 ICC [µA] 450 400 3.0V 350 2.7V 300 250 2.2V 200 1.8V 150 100 50 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 33-2. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 11 10 3.6V 9 ICC [mA] 8 3.0V 7 2.7V 6 5 4 2.
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Figure 33-3. Active mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 180 160 -40°C Icc [µA] 140 25°C 85°C 105°C 120 100 80 60 40 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-4. Active mode supply current vs. VCC. fSYS = 1MHz external clock. 600 -40°C 25°C 85°C 105°C 550 500 Icc [µA] 450 400 350 300 250 200 150 100 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-5. Active mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 1350 1200 -40°C 25 °C 85°C 105°C 1050 Icc [µA] 900 750 600 450 300 150 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-6. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 5.0 -40°C 25 °C 85°C 105°C 4.5 4.0 Icc [mA] 3.5 3.0 2.5 2.0 1.5 1.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-7. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator. 12.0 -40 °C 11.5 11.0 25 °C 10.5 85 °C 105°C 10.0 Icc [mA] 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 33.1.1.2 Idle mode supply current Figure 33-8. Idle mode supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 120 3.6V 105 90 3.0V ICC[uA] 75 2.7V 60 2.2V 45 1.8V 30 15 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
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Figure 33-9. Idle mode supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 4.0 3.6 3.6V 3.2 Icc [mA] 2.8 3.0V 2.4 2.7V 2.0 1.6 1.2 2.2V 0.8 1.8V 0.4 0.0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Frenquecy [MHz] Figure 33-10. Idle mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 35.50 105°C 34.75 34.00 33.25 32.50 Icc [µA] 31.75 85°C 31.00 -40°C 30.25 25 °C 29.50 28.75 28.00 27.25 26.50 25.75 25.00 1.6 1.8 2 2.2 2.4 2.6 2.
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Figure 33-11. Idle mode supply current vs. VCC. fSYS = 1MHz external clock. 130 105°C 85 °C 25 °C -40°C 120 110 100 Icc [µA] 90 80 70 60 50 40 30 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-12. Idle mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 330 -40°C 25°C 85 °C 105 °C 310 290 270 Icc [µA] 250 230 210 190 170 150 130 110 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-13. Idle mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 1600 -40 °C 25 °C 85°C 105°C 1500 1400 1300 Icc [µA] 1200 1100 1000 900 800 700 600 500 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-14. Idle mode current vs. VCC. fSYS = 32MHz internal oscillator. 4.25 -40°C 4.00 25 °C 85°C 105°C 3.75 Icc [mA] 3.50 3.25 3.00 2.75 2.50 2.25 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.
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33.1.1.3 Power-down mode supply current Figure 33-15. Power-down mode supply current vs. VCC. All functions disabled. 6.5 105°C 6.0 5.5 5.0 Icc [µA] 4.5 4.0 3.5 85°C 3.0 2.5 2.0 25°C -40°C 1.5 1.0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-16. Power-down mode supply current vs. VCC. Watchdog and sampled BOD enabled. 5.5 105°C 5.0 4.5 4.0 Icc [µA] 3.5 3.0 2.5 2.0 85°C 1.5 1.0 0.5 25°C -40°C 0.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-17. Power-down mode supply current vs. Temperature. Watchdog and sampled BOD enabled and running from internal ULP oscillator. 7.5 7.0 3.6V 6.5 3.0V 2.7V 2.2V 1.8V 6.0 5.5 Icc [µA] 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] 33.1.1.4 Power-save mode supply current Figure 33-18. Power-save mode supply current vs.VCC. Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC. 0.9 Normal mode 0.
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33.1.1.5 Standby mode supply current Figure 33-19. Standby supply current vs. VCC. Standby, fSYS = 1MHz. 12.1 105°C 10.9 9.7 85°C I CC [µA] 8.5 25°C -40°C 7.3 6.1 4.9 3.7 2.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-20. Standby supply current vs. VCC. 25°C, running from different crystal oscillators. 480 16MHz 12MHz 440 ICC [µA] 400 360 320 8MHz 2MHz 280 240 0.454MHz 200 160 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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33.1.2 I/O Pin Characteristics 33.1.2.1 Pull-up Figure 33-21. I/O pin pull-up resistor current vs. input voltage. VCC = 1.8V. 72 64 56 IPIN [µA] 48 40 32 24 -40°C 25°C 85°C 105°C 16 8 0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 VPIN [V] Figure 33-22. I/O pin pull-up resistor current vs. input voltage. VCC = 3.0V. 120 108 96 IPIN [µA] 84 72 60 48 36 -40°C 25°C 85°C 105°C 24 12 0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.
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Figure 33-23. I/O pin pull-up resistor current vs. input voltage. VCC = 3.3V. 135 120 105 IPIN [µA] 90 75 60 45 30 -40°C 25°C 85°C 105°C 15 0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 VPIN [V] 33.1.2.2 Output Voltage vs. Sink/Source Current Figure 33-24. I/O pin output voltage vs. source current. VCC = 1.8V. 2.0 1.8 1.6 VPIN [V] 1.4 1.2 1.0 0.8 0.6 0.4 85°C 105°C 25°C -40°C 0.2 0 -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.
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Figure 33-25. I/O pin output voltage vs. source current. VCC = 3.0V. 3.15 2.80 2.45 VPIN [V] 2.10 1.75 1.40 1.05 25°C -40°C 85°C 105°C 0.70 0.35 0 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] Figure 33-26. I/O pin output voltage vs. source current. VCC = 3.3V. 3.5 3.15 2.8 VPIN [V] 2.45 2.1 1.75 1.4 1.05 0.7 25°C -40°C 85°C 105°C 0.
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Figure 33-27. I/O pin output voltage vs. source current. 4 VPIN [V] 3.65 3.3 3.6V 3.3V 2.95 3.0V 2.7V 2.6 2.25 1.9 1.8V 1.6V 1.55 1.2 0.85 0.5 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] Figure 33-28. I/O pin output voltage vs. sink current. VCC = 1.8V. 1 0.9 0.8 105°C VPIN [V] 0.7 25°C 85°C -40°C 0.6 0.5 0.4 0.3 0.2 0.
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Figure 33-29. I/O pin output voltage vs. sink current. VCC = 3.0V. 1.1 105°C 85°C 1.0 0.9 25°C 0.8 -40°C VPIN [V] 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 IPIN [mA] Figure 33-30. I/O pin output voltage vs. sink current. VCC = 3.3V. VPIN [V] 1 0.9 105°C 85°C 0.8 25°C 0.7 -40°C 0.6 0.5 0.4 0.3 0.2 0.
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Figure 33-31. I/O pin output voltage vs. sink current. 1.5 1.8V 1.6V 1.35 2.7V 3.0V 3.3V 3.6V 1.2 VPIN [V] 1.05 0.9 0.75 0.6 0.45 0.3 0.15 0 0 2 4 6 8 10 12 14 16 18 20 IPIN [mA] 33.1.2.3 Thresholds and Hysteresis Figure 33-32. I/O pin input threshold voltage vs. VCC. T = 25C. 1.8 VIH Vthreshold [V] 1.7 1.6 VIL 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-33. I/O pin input threshold voltage vs. VCC. VIH I/O pin read as “1”. -40°C 25°C 85 °C 105 °C 1.8 1.7 Vthreshold [V] 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-34. I/O pin input threshold voltage vs. VCC. VIL I/O pin read as “0”. 1.75 -40°C 25°C 85 °C 105 °C 1.60 Vthreshold [V] 1.45 1.30 1.15 1.00 0.85 0.70 0.55 0.40 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-35. I/O pin input hysteresis vs. VCC. 0.42 0.39 -40°C Vthreshold [V] 0.36 0.33 0.3 25°C 0.27 0.24 85°C 0.21 105°C 0.18 0.15 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 2.4 2.6 2.8 3.0 VCC [V] 33.1.3 ADC Characteristics Figure 33-36. INL error vs. external VREF. T = 25C, VCC = 3.6V, external reference. 1.6 1.4 INL[LSB] 1.2 Single-ended unsigned mode 1.0 0.8 0.6 Differential mode 0.4 Single-ended signed mode 0.2 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.
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Figure 33-37. INL error vs. sample rate. T = 25C, VCC = 3.6V, VREF = 3.0V external. 0.70 0.65 Single-ended unsigned mode INL[LSB] 0.60 0.55 Differential mode 0.50 0.45 0.40 0.35 Single-ended signed mode 0.30 0.25 50 100 150 200 250 300 ADC sample rate [ksps] Figure 33-38. INL error vs. input code. 1.25 1.00 0.75 INL[LSB] 0.50 0.25 0.00 -0.25 -0.50 -0.75 -1.00 -1.
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Figure 33-39. DNL error vs. external VREF. T = 25C, VCC = 3.6V, external reference. 0.70 0.65 0.60 Single-ended unsigned mode DNL [LSB] 0.55 0.50 0.45 0.40 Differential mode 0.35 Single-ended signed mode 0.30 0.25 0.20 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] Figure 33-40. DNL error vs. sample rate. T = 25C, VCC = 3.6V, VREF = 3.0V external. 0.60 0.55 Single-ended unsigned mode DNL [LSB] 0.50 0.45 0.40 Differential mode 0.35 0.30 Single-ended signed mode 0.25 0.
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Figure 33-41. DNL error vs. input code. 1 DNL [LSB] 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code Figure 33-42. Gain error vs. VREF. T = 25C, VCC = 3.6V, ADC sample rate = 200ksps. -5 Gain error [mV] -6 -7 Differential mode -8 -9 Single-ended signed mode -10 -11 -12 Single-ended unsigned mode -13 -14 -15 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 33-43. Gain error vs. VCC. T = 25C, VREF = external 1.0V, ADC sample rate = 200ksps. -2 Gain error [mV] -3 -4 Differential mode -5 Single-ended signed mode -6 Single-ended unsigned mode -7 -8 -9 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-44. Offset error vs. VREF. T = 25C, VCC = 3.6V, ADC sample rate = 200ksps. 9.4 9.2 Offset error [mV] 9.0 8.8 Differential mode 8.6 8.4 8.2 8.0 7.8 7.6 7.4 7.2 7.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 33-45. Gain error vs. temperature. VCC = 3.0V, VREF = external 2.0V. 0 -2 Gain error [mV] Single-ended signed mode -4 -6 Differential mode -8 -10 Single-ended unsigned mode -12 -14 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-46. Offset error vs. VCC. T = 25C, VREF = external 1.0V, ADC sample rate = 200ksps. 8.00 Offset error [mV] 7.00 6.00 5.00 Differential mode 4.00 3.00 2.00 1.00 0.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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33.1.4 Analog Comparator Characteristics Figure 33-47. Analog comparator hysteresis vs. VCC. High speed, small hysteresis. VHYST [mV] 14 13 105°C 12 85°C 11 10 25°C 9 8 7 -40°C 6 5 4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-48. Analog comparator hysteresis vs. VCC. High speed, large hysteresis. 32 105°C 85°C 30 VHYST [mV] 28 26 25°C 24 22 -40°C 20 18 16 14 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-49. Analog comparator hysteresis vs. VCC. Low power, small hysteresis. 30 28 105°C 85°C VHYST [mV] 26 24 25°C 22 -40°C 20 18 16 14 12 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-50. Analog comparator hysteresis vs. VCC. Low power, large hysteresis. 68 64 105°C 85°C 60 VHYST [mV] 56 25°C 52 48 -40°C 44 40 36 32 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-51. Analog comparator current source vs. calibration value. T = 25C. 8 ICURRENTSOURCE [µA] 7.25 6.5 5.75 5 3.6V 4.25 3.0V 3.5 2.2V 2.75 1.8V 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CALIBA [3..0] Figure 33-52. Analog comparator current source vs. calibration value. VCC = 3.0V. 7.0 6.6 ICURRENTSOURCE [µA] 6.2 5.8 5.4 5.0 4.6 4.2 -40°C 25°C 85°C 105°C 3.8 3.4 3.0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CALIBA [3..
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Figure 33-53. Voltage scaler INL vs. SCALEFAC. T = 25C, VCC = 3.0V. 0.050 0.025 INL [LSB] 0 -0.025 -0.050 -0.075 -0.100 25°C -0.125 -0.150 0 10 20 30 40 50 60 70 SCALEFAC 33.1.5 Internal 1.0V reference Characteristics Bandgap Voltage [V] Figure 33-54. ADC Internal 1.0V reference vs. temperature. 1.0088 1.008 1.0072 1.0064 1.0056 1.0048 1.004 1.0032 1.0024 1.0016 1.0008 1 0.9992 0.9984 0.9976 0.9968 1.8V 2.2V 2.7V 3.0V 3.
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33.1.6 BOD Characteristics Figure 33-55. BOD thresholds vs. temperature. BOD level = 1.6V. 1.574 Rising Vcc 1.57 Falling Vcc 1.566 VBOT [V] 1.562 1.558 1.554 1.55 1.546 1.542 1.538 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 95 105 Temperature [°C] Figure 33-56. BOD thresholds vs. temperature. BOD level = 3.0V. 2.992 2.984 Rising Vcc 2.976 VBOT [V] 2.968 2.96 2.952 2.944 Falling Vcc 2.936 2.928 2.
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33.1.7 External Reset Characteristics Figure 33-57. Minimum Reset pin pulse width vs. VCC. 145 140 135 130 TRST [ns] 125 120 115 110 105 105°C 85°C 100 95 25°C -40°C 90 85 80 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-58. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 80 72 64 IRESET [µA] 56 48 40 32 24 16 -40°C 25°C 85°C 105°C 8 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
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Figure 33-59. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 135 120 IRESET [µA] 105 90 75 60 45 30 -40°C 25°C 85°C 105°C 15 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 VRESET [V] Figure 33-60. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 150 135 120 IRESET [µA] 105 90 75 60 45 30 -40°C 25°C 85°C 105°C 15 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.
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Figure 33-61. Reset pin input threshold voltage vs. VCC. VIH - Reset pin read as “1”. -40°C 25°C 85°C 105°C 2.10 2.00 1.90 1.80 V threshold [V] 1.70 1.60 1.50 1.40 1.30 1.20 1.10 1.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-62. Reset pin input threshold voltage vs. VCC. VIL - Reset pin read as “0”. 1.7 -40°C 25°C 85 °C 105 °C 1.6 1.5 Vthreshold [V] 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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33.1.8 Power-on Reset Characteristics I CC [µA] Figure 33-63. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in continuous mode. 700 -40°C 600 25°C 500 85°C 105°C 400 300 200 100 0 0.4 0.7 1.0 1.3 1.6 1.9 2.2 2.5 2.8 VCC [V] Figure 33-64. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in sampled mode. 650 -40°C 585 520 25°C 85°C 105°C I CC [µA] 455 390 325 260 195 130 65 0 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.
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33.1.9 Oscillator Characteristics 33.1.9.1 Ultra Low-Power internal oscillator Frequency [kHz] Figure 33-65. Ultra Low-Power internal oscillator frequency vs. temperature. 35.4 35.1 34.8 34.5 34.2 33.9 33.6 33.3 33.0 32.7 32.4 32.1 31.8 31.5 31.2 30.9 3.6V 3.3V 3.0V 2.7V 2.0V 1.8V -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] 33.1.9.2 32.768kHz Internal Oscillator Figure 33-66. 32.768kHz internal oscillator frequency vs. temperature. 32.9 3.6V 3.3V 3.0V 2.7V 2.
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Figure 33-67. 32.768kHz internal oscillator frequency vs. calibration value. VCC = 3.0V, T = 25°C. 55 51 3.0V Frequency [kHz] 47 43 39 35 31 27 23 19 15 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 RC32KCAL [7..0] 33.1.9.3 2MHz Internal Oscillator Figure 33-68. 2MHz internal oscillator frequency vs. temperature. DFLL disabled. 2.16 2.14 Frequency [MHz] 2.12 2.10 2.08 2.06 2.04 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 2.02 2.00 1.98 1.96 1.
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Figure 33-69. 2MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator . 2.012 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 2.008 Frequency [MHz] 2.004 2.00 1.996 1.992 1.988 1.984 1.98 1.976 1.972 1.968 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Step Size [%] Figure 33-70. 2MHz internal oscillator CALA calibration step size. VCC = 3V. 0.29 0.28 0.27 0.26 0.25 0.24 0.23 0.22 0.21 0.20 0.19 0.18 0.17 0.16 0.15 0.14 0.13 0.
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33.1.9.4 32MHz Internal Oscillator Figure 33-71. 32MHz internal oscillator frequency vs. temperature. DFLL disabled. 36.45 36 Frequency [MHz] 35.55 35.1 34.65 34.2 33.75 33.3 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 32.85 32.4 31.95 31.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-72. 32MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.15 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 32.1 32.05 Frequency [MHz] 32 31.
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Figure 33-73. 32MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.34 0.32 0.30 Step Size [%] 0.28 0.26 0.24 0.22 0.20 0.16 -40°C 105°C 85°C 0.14 25°C 0.18 0.12 0 10 20 30 40 50 60 70 80 90 100 110 120 130 CALA 33.1.9.5 32MHz internal oscillator calibrated to 48MHz Figure 33-74. 48MHz internal oscillator frequency vs. temperature. DFLL disabled. 55.3 54.6 53.9 Frequency [MHz] 53.2 52.5 51.8 51.1 50.4 49.7 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 49.0 48.3 47.6 46.9 46.
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Figure 33-75. 48MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.15 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 32.1 32.05 Frequency [MHz] 32 31.95 31.9 31.85 31.8 31.75 31.7 31.65 31.6 31.55 31.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-76. 48MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.29 0.27 Step Size [%] 0.25 0.23 0.21 0.19 -40°C 0.17 25°C 105°C 0.15 0.13 85°C 0.11 0.
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33.1.10 Two-Wire Interface characteristics Figure 33-77. SDA hold time vs. temperature. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-78. SDA hold time vs. supply voltage. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
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33.1.11 PDI characteristics Figure 33-79. Maximum PDI frequency vs. VCC. 22 21 -40°C Frequency max [MHz] 20 19 25°C 18 85°C 105°C 17 16 15 14 13 12 11 10 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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33.2 ATxmega32D4 33.2.1 Current consumption 33.2.1.1 Active mode supply current Figure 33-80. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 600 550 3.6V 500 ICC [µA] 450 400 3.0V 350 2.7V 300 250 2.2V 200 1.8V 150 100 50 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 33-81. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 11 10 3.6V 9 ICC [mA] 8 3.0V 7 2.7V 6 5 4 2.2V 3 2 1.
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Figure 33-82. Active mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 180 160 -40°C Icc [µA] 140 25°C 85°C 105°C 120 100 80 60 40 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-83. Active mode supply current vs. VCC. fSYS = 1MHz external clock. 600 -40°C 25°C 85°C 105°C 550 500 Icc [µA] 450 400 350 300 250 200 150 100 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-84. Active mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 1350 1200 -40°C 25 °C 85°C 105°C 1050 Icc [µA] 900 750 600 450 300 150 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-85. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 5.0 -40°C 25 °C 85°C 105°C 4.5 4.0 Icc [mA] 3.5 3.0 2.5 2.0 1.5 1.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-86. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator. 12.0 -40 °C 11.5 11.0 25 °C 10.5 85 °C 105°C 10.0 Icc [mA] 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 33.2.1.2 Idle mode supply current Figure 33-87. Idle mode supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 120 3.6V 105 90 3.0V ICC[uA] 75 2.7V 60 2.2V 45 1.8V 30 15 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
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Figure 33-88. Idle mode supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 4.0 3.6 3.6V 3.2 Icc [mA] 2.8 3.0V 2.4 2.7V 2.0 1.6 1.2 2.2V 0.8 1.8V 0.4 0.0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Frenquecy [MHz] Figure 33-89. Idle mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 35.50 105°C 34.75 34.00 33.25 32.50 Icc [µA] 31.75 85°C 31.00 -40°C 30.25 25 °C 29.50 28.75 28.00 27.25 26.50 25.75 25.00 1.6 1.8 2 2.2 2.4 2.6 2.
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Figure 33-90. Idle mode supply current vs. VCC. fSYS = 1MHz external clock. 130 105°C 85 °C 25 °C -40°C 120 110 100 Icc [µA] 90 80 70 60 50 40 30 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-91. Idle mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 330 -40°C 25°C 85 °C 105 °C 310 290 270 Icc [µA] 250 230 210 190 170 150 130 110 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-92. Idle mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 1600 -40 °C 25 °C 85°C 105°C 1500 1400 1300 Icc [µA] 1200 1100 1000 900 800 700 600 500 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-93. Idle mode current vs. VCC. fSYS = 32MHz internal oscillator. 4.25 -40°C 4.00 25 °C 85°C 105°C 3.75 Icc [mA] 3.50 3.25 3.00 2.75 2.50 2.25 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.
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33.2.1.3 Power-down mode supply current Figure 33-94. Power-down mode supply current vs. VCC. All functions disabled. 6.5 105°C 6.0 5.5 5.0 Icc [µA] 4.5 4.0 3.5 85°C 3.0 2.5 2.0 25°C -40°C 1.5 1.0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-95. Power-down mode supply current vs. VCC. Watchdog and sampled BOD enabled. 5.5 105°C 5.0 4.5 4.0 Icc [µA] 3.5 3.0 2.5 2.0 85°C 1.5 1.0 0.5 25°C -40°C 0.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-96. Power-down mode supply current vs. Temperature. Watchdog and sampled BOD enabled and running from internal ULP oscillator. 7.5 7.0 3.6V 6.5 3.0V 2.7V 2.2V 1.8V 6.0 5.5 Icc [µA] 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] 33.2.1.4 Power-save mode supply current Figure 33-97. Power-save mode supply current vs.VCC. Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC. 0.9 Normal mode 0.
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33.2.1.5 Standby mode supply current Figure 33-98. Standby supply current vs. VCC. Standby, fSYS = 1MHz. 12.1 105°C 10.9 9.7 85°C I CC [µA] 8.5 25°C -40°C 7.3 6.1 4.9 3.7 2.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-99. Standby supply current vs. VCC. 25°C, running from different crystal oscillators. 480 16MHz 12MHz 440 ICC [µA] 400 360 320 8MHz 2MHz 280 240 0.454MHz 200 160 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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33.2.2 I/O Pin Characteristics 33.2.2.1 Pull-up Figure 33-100. I/O pin pull-up resistor current vs. input voltage. VCC = 1.8V. 72 64 56 IPIN [µA] 48 40 32 24 -40°C 25°C 85°C 105°C 16 8 0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 VPIN [V] Figure 33-101. I/O pin pull-up resistor current vs. input voltage. VCC = 3.0V. 120 108 96 IPIN [µA] 84 72 60 48 36 -40°C 25°C 85°C 105°C 24 12 0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.
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Figure 33-102. I/O pin pull-up resistor current vs. input voltage. VCC = 3.3V. 135 120 105 IPIN [µA] 90 75 60 45 30 -40°C 25°C 85°C 105°C 15 0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 VPIN [V] 33.2.2.2 Output Voltage vs. Sink/Source Current Figure 33-103. I/O pin output voltage vs. source current. VCC = 1.8V. 2.0 1.8 1.6 VPIN [V] 1.4 1.2 1.0 0.8 0.6 0.4 85°C 105°C 25°C -40°C 0.2 0 -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.
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Figure 33-104. I/O pin output voltage vs. source current. VCC = 3.0V. 3.15 2.80 2.45 VPIN [V] 2.10 1.75 1.40 1.05 25°C -40°C 85°C 105°C 0.70 0.35 0 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] Figure 33-105. I/O pin output voltage vs. source current. VCC = 3.3V. 3.5 3.15 2.8 VPIN [V] 2.45 2.1 1.75 1.4 1.05 0.7 25°C -40°C 85°C 105°C 0.
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Figure 33-106. I/O pin output voltage vs. source current. 4 VPIN [V] 3.65 3.3 3.6V 3.3V 2.95 3.0V 2.7V 2.6 2.25 1.9 1.8V 1.6V 1.55 1.2 0.85 0.5 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] Figure 33-107. I/O pin output voltage vs. sink current. VCC = 1.8V. 1 0.9 0.8 105°C VPIN [V] 0.7 25°C 85°C -40°C 0.6 0.5 0.4 0.3 0.2 0.
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Figure 33-108. I/O pin output voltage vs. sink current. VCC = 3.0V. 1.1 105°C 85°C 1.0 0.9 25°C 0.8 -40°C VPIN [V] 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 IPIN [mA] Figure 33-109. I/O pin output voltage vs. sink current. VCC = 3.3V. VPIN [V] 1 0.9 105°C 85°C 0.8 25°C 0.7 -40°C 0.6 0.5 0.4 0.3 0.2 0.
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Figure 33-110. I/O pin output voltage vs. sink current. 1.5 1.8V 1.6V 1.35 2.7V 3.0V 3.3V 3.6V 1.2 VPIN [V] 1.05 0.9 0.75 0.6 0.45 0.3 0.15 0 0 2 4 6 8 10 12 14 16 18 20 IPIN [mA] 33.2.2.3 Thresholds and Hysteresis Figure 33-111. I/O pin input threshold voltage vs. VCC. T = 25C. 1.8 VIH Vthreshold [V] 1.7 1.6 VIL 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-112. I/O pin input threshold voltage vs. VCC. VIH I/O pin read as “1”. -40°C 25°C 85 °C 105 °C 1.8 1.7 Vthreshold [V] 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-113. I/O pin input threshold voltage vs. VCC. VIL I/O pin read as “0”. 1.75 -40°C 25°C 85 °C 105 °C 1.60 Vthreshold [V] 1.45 1.30 1.15 1.00 0.85 0.70 0.55 0.40 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-114. I/O pin input hysteresis vs. VCC. 0.42 0.39 -40°C Vthreshold [V] 0.36 0.33 0.3 25°C 0.27 0.24 85°C 0.21 105°C 0.18 0.15 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 2.4 2.6 2.8 3.0 VCC [V] 33.2.3 ADC Characteristics Figure 33-115. INL error vs. external VREF. T = 25C, VCC = 3.6V, external reference. 1.6 1.4 INL[LSB] 1.2 Single-ended unsigned mode 1.0 0.8 0.6 Differential mode 0.4 Single-ended signed mode 0.2 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.
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Figure 33-116. INL error vs. sample rate. T = 25C, VCC = 3.6V, VREF = 3.0V external. 0.70 0.65 Single-ended unsigned mode INL[LSB] 0.60 0.55 Differential mode 0.50 0.45 0.40 0.35 Single-ended signed mode 0.30 0.25 50 100 150 200 250 300 ADC sample rate [ksps] Figure 33-117. INL error vs. input code. 1.25 1.00 0.75 INL[LSB] 0.50 0.25 0.00 -0.25 -0.50 -0.75 -1.00 -1.
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Figure 33-118. DNL error vs. external VREF. T = 25C, VCC = 3.6V, external reference. 0.70 0.65 0.60 Single-ended unsigned mode DNL [LSB] 0.55 0.50 0.45 0.40 Differential mode 0.35 Single-ended signed mode 0.30 0.25 0.20 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] Figure 33-119. DNL error vs. sample rate. T = 25C, VCC = 3.6V, VREF = 3.0V external. 0.60 0.55 Single-ended unsigned mode DNL [LSB] 0.50 0.45 0.40 Differential mode 0.35 0.30 Single-ended signed mode 0.25 0.
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Figure 33-120. DNL error vs. input code. 1 DNL [LSB] 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code Figure 33-121. Gain error vs. VREF. T = 25C, VCC = 3.6V, ADC sample rate = 200ksps. -5 Gain error [mV] -6 -7 Differential mode -8 -9 Single-ended signed mode -10 -11 -12 Single-ended unsigned mode -13 -14 -15 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 33-122. Gain error vs. VCC. T = 25C, VREF = external 1.0V, ADC sample rate = 200ksps. -2 Gain error [mV] -3 -4 Differential mode -5 Single-ended signed mode -6 Single-ended unsigned mode -7 -8 -9 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-123. Offset error vs. VREF. T = 25C, VCC = 3.6V, ADC sample rate = 200ksps. 9.4 9.2 Offset error [mV] 9.0 8.8 Differential mode 8.6 8.4 8.2 8.0 7.8 7.6 7.4 7.2 7.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 33-124. Gain error vs. temperature. VCC = 3.0V, VREF = external 2.0V. 0 -2 Gain error [mV] Single-ended signed mode -4 -6 Differential mode -8 -10 Single-ended unsigned mode -12 -14 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-125. Offset error vs. VCC. T = 25C, VREF = external 1.0V, ADC sample rate = 200ksps. 8.00 Offset error [mV] 7.00 6.00 5.00 Differential mode 4.00 3.00 2.00 1.00 0.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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33.2.4 Analog Comparator Characteristics Figure 33-126. Analog comparator hysteresis vs. VCC. High speed, small hysteresis. VHYST [mV] 14 13 105°C 12 85°C 11 10 25°C 9 8 7 -40°C 6 5 4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-127. Analog comparator hysteresis vs. VCC. High speed, large hysteresis. 32 105°C 85°C 30 VHYST [mV] 28 26 25°C 24 22 -40°C 20 18 16 14 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-128. Analog comparator hysteresis vs. VCC. Low power, small hysteresis. 30 28 105°C 85°C VHYST [mV] 26 24 25°C 22 -40°C 20 18 16 14 12 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-129. Analog comparator hysteresis vs. VCC. Low power, large hysteresis. 68 64 105°C 85°C 60 VHYST [mV] 56 25°C 52 48 -40°C 44 40 36 32 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-130. Analog comparator current source vs. calibration value. T = 25C. 8 ICURRENTSOURCE [µA] 7.25 6.5 5.75 5 3.6V 4.25 3.0V 3.5 2.2V 2.75 1.8V 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CALIBA [3..0] Figure 33-131. Analog comparator current source vs. calibration value. VCC = 3.0V. 7.0 6.6 ICURRENTSOURCE [µA] 6.2 5.8 5.4 5.0 4.6 4.2 -40°C 25°C 85°C 105°C 3.8 3.4 3.0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CALIBA [3..
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Figure 33-132. Voltage scaler INL vs. SCALEFAC. T = 25C, VCC = 3.0V. 0.050 0.025 INL [LSB] 0 -0.025 -0.050 -0.075 -0.100 25°C -0.125 -0.150 0 10 20 30 40 50 60 70 SCALEFAC 33.2.5 Internal 1.0V reference Characteristics Bandgap Voltage [V] Figure 33-133. ADC Internal 1.0V reference vs. temperature. 1.0088 1.008 1.0072 1.0064 1.0056 1.0048 1.004 1.0032 1.0024 1.0016 1.0008 1 0.9992 0.9984 0.9976 0.9968 1.8V 2.2V 2.7V 3.0V 3.
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33.2.6 BOD Characteristics Figure 33-134. BOD thresholds vs. temperature. BOD level = 1.6V. 1.574 Rising Vcc 1.57 Falling Vcc 1.566 VBOT [V] 1.562 1.558 1.554 1.55 1.546 1.542 1.538 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 95 105 Temperature [°C] Figure 33-135. BOD thresholds vs. temperature. BOD level = 3.0V. 2.992 2.984 Rising Vcc 2.976 VBOT [V] 2.968 2.96 2.952 2.944 Falling Vcc 2.936 2.928 2.
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33.2.7 External Reset Characteristics Figure 33-136. Minimum Reset pin pulse width vs. VCC. 145 140 135 130 TRST [ns] 125 120 115 110 105 105°C 85°C 100 95 25°C -40°C 90 85 80 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-137. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 80 72 64 IRESET [µA] 56 48 40 32 24 16 -40°C 25°C 85°C 105°C 8 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
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Figure 33-138. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 135 120 IRESET [µA] 105 90 75 60 45 30 -40°C 25°C 85°C 105°C 15 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 VRESET [V] Figure 33-139. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 150 135 120 IRESET [µA] 105 90 75 60 45 30 -40°C 25°C 85°C 105°C 15 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.
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Figure 33-140. Reset pin input threshold voltage vs. VCC. VIH - Reset pin read as “1”. -40°C 25°C 85°C 105°C 2.10 2.00 1.90 1.80 V threshold [V] 1.70 1.60 1.50 1.40 1.30 1.20 1.10 1.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-141. Reset pin input threshold voltage vs. VCC. VIL - Reset pin read as “0”. 1.7 -40°C 25°C 85 °C 105 °C 1.6 1.5 Vthreshold [V] 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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33.2.8 Power-on Reset Characteristics I CC [µA] Figure 33-142. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in continuous mode. 700 -40°C 600 25°C 500 85°C 105°C 400 300 200 100 0 0.4 0.7 1.0 1.3 1.6 1.9 2.2 2.5 2.8 VCC [V] Figure 33-143. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in sampled mode. 650 -40°C 585 520 25°C 85°C 105°C I CC [µA] 455 390 325 260 195 130 65 0 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.
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33.2.9 Oscillator Characteristics 33.2.9.1 Ultra Low-Power internal oscillator Frequency [kHz] Figure 33-144. Ultra Low-Power internal oscillator frequency vs. temperature. 35.4 35.1 34.8 34.5 34.2 33.9 33.6 33.3 33.0 32.7 32.4 32.1 31.8 31.5 31.2 30.9 3.6V 3.3V 3.0V 2.7V 2.0V 1.8V -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] 33.2.9.2 32.768kHz Internal Oscillator Figure 33-145. 32.768kHz internal oscillator frequency vs. temperature. 32.9 3.6V 3.3V 3.0V 2.7V 2.
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Figure 33-146. 32.768kHz internal oscillator frequency vs. calibration value. VCC = 3.0V, T = 25°C. 55 51 3.0V Frequency [kHz] 47 43 39 35 31 27 23 19 15 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 RC32KCAL [7..0] 33.2.9.3 2MHz Internal Oscillator Figure 33-147. 2MHz internal oscillator frequency vs. temperature. DFLL disabled. 2.16 2.14 Frequency [MHz] 2.12 2.10 2.08 2.06 2.04 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 2.02 2.00 1.98 1.96 1.
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Figure 33-148. 2MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator . 2.012 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 2.008 Frequency [MHz] 2.004 2.00 1.996 1.992 1.988 1.984 1.98 1.976 1.972 1.968 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Step Size [%] Figure 33-149. 2MHz internal oscillator CALA calibration step size. VCC = 3V. 0.29 0.28 0.27 0.26 0.25 0.24 0.23 0.22 0.21 0.20 0.19 0.18 0.17 0.16 0.15 0.14 0.13 0.
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33.2.9.4 32MHz Internal Oscillator Figure 33-150. 32MHz internal oscillator frequency vs. temperature. DFLL disabled. 36.45 36 Frequency [MHz] 35.55 35.1 34.65 34.2 33.75 33.3 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 32.85 32.4 31.95 31.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-151. 32MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.15 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 32.1 32.05 Frequency [MHz] 32 31.
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Figure 33-152. 32MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.34 0.32 0.30 Step Size [%] 0.28 0.26 0.24 0.22 0.20 0.16 -40°C 105°C 85°C 0.14 25°C 0.18 0.12 0 10 20 30 40 50 60 70 80 90 100 110 120 130 CALA 33.2.9.5 32MHz internal oscillator calibrated to 48MHz Figure 33-153. 48MHz internal oscillator frequency vs. temperature. DFLL disabled. 55.3 54.6 53.9 Frequency [MHz] 53.2 52.5 51.8 51.1 50.4 49.7 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 49.0 48.3 47.6 46.9 46.
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Figure 33-154. 48MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.15 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 32.1 32.05 Frequency [MHz] 32 31.95 31.9 31.85 31.8 31.75 31.7 31.65 31.6 31.55 31.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-155. 48MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.29 0.27 Step Size [%] 0.25 0.23 0.21 0.19 -40°C 0.17 25°C 105°C 0.15 0.13 85°C 0.11 0.
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33.2.10 Two-Wire Interface characteristics Figure 33-156. SDA hold time vs. temperature. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-157. SDA hold time vs. supply voltage. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
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33.2.11 PDI characteristics Figure 33-158. Maximum PDI frequency vs. VCC. 22 21 -40°C Frequency max [MHz] 20 19 25°C 18 85°C 105°C 17 16 15 14 13 12 11 10 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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33.3 ATxmega64D4 33.3.1 Current consumption 33.3.1.1 Active mode supply current Figure 33-159. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 700 3.6 V 600 ICC [µA] 500 3.0 V 400 2.7 V 300 2.2 V 200 1.8 V 1.6 V 100 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 33-160. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 12 3.6 V 10 3.0 V ICC [mA] 8 2.7 V 6 4 2.2 V 2 1.8 V 1.
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Figure 33-161. Active mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 250 -40°C 230 25°C 210 85°C ICC [µA] 190 170 150 130 110 90 70 50 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-162. Active mode supply current vs. VCC. fSYS = 1MHz external clock. 680 -40°C 25°C 85°C 630 580 ICC [µA] 530 480 430 380 330 280 230 180 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-163. Active mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 1300 -40°C 25°C 85°C 1200 1100 ICC [µA] 1000 900 800 700 600 500 400 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-164. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 4.8 -40°C 25°C 85°C 4.4 4.0 ICC [mA] 3.6 3.2 2.8 2.4 2.0 1.6 1.2 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-165. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator. 12.0 -40°C 11.5 25°C 85°C 11.0 ICC [mA] 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 33.3.1.2 Idle mode supply current Figure 33-166. Idle mode supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 150 3.6 V 135 ICC [µA] 120 105 3.0 V 90 2.7 V 75 2.2 V 60 1.8 V 1.6 V 45 30 15 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
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Figure 33-167. Idle mode supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 5.0 4.5 3.6 V ICC [mA] 4.0 3.5 3.0 V 3.0 2.7 V 2.5 2.0 2.2 V 1.5 1.0 1.8 V 1.6 V 0.5 0.0 0 4 8 12 16 20 24 28 32 Frequency [MHz] Figure 33-168. Idle mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 34.0 -40°C 33.3 85°C 25°C 32.5 ICC [µA] 31.8 31.0 30.3 29.5 28.8 28.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-169. Idle mode supply current vs. VCC. fSYS = 1MHz external clock. 153 85°C 25°C -40°C 141 129 ICC [µA] 117 105 93 81 69 57 45 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-170. Idle mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 400 -40°C 85°C 25°C 375 350 ICC [µA] 325 300 275 250 225 200 175 150 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-171. Idle mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 18.5 -40°C 25°C 85°C 17.0 15.5 ICC [mA] 14.0 12.5 11.0 0.95 0.80 0.65 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-172. Idle mode current vs. VCC. fSYS = 32MHz internal oscillator. 5.1 4.9 -40°C 4.7 25°C 85°C ICC [mA] 4.5 4.3 4.1 3.9 3.7 3.5 3.3 3.1 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.
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33.3.1.3 Power-down mode supply current Figure 33-173. Power-down mode supply current vs. temperature. All functions disabled. 1.0 0.9 3.6 V 0.8 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V ICC [µA] 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-174. Power-down mode supply current vs. VCC. All functions disabled. 1.0 0.9 85°C 0.8 ICC [µA] 0.7 0.6 0.5 0.4 0.3 0.2 0.1 25°C 0.0 -40°C 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-175. Power-down mode supply current vs. VCC. Watchdog and sampled BOD enabled. 2.35 85°C 2.20 2.05 ICC [µA] 1.90 1.75 1.60 25°C -40°C 1.45 1.30 1.15 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 33.3.1.4 Power-save mode supply current Figure 33-176. Power-save mode supply current vs.VCC. Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC. 0.9 Normal mode 0.8 0.7 ICC [µA] 0.6 Low-power mode 0.5 0.4 0.3 0.2 0.1 0 1.6 1.8 2.0 2.2 2.4 2.6 2.
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33.3.1.5 Standby mode supply current Figure 33-177. Standby supply current vs. VCC. Standby, fSYS = 1MHz. 9.5 85°C 9.0 8.5 25°C -40°C 8.0 ICC [µA] 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-178. Standby supply current vs. VCC. 25°C, running from different crystal oscillators. 480 16MHz 12MHz 440 ICC [µA] 400 360 320 8MHz 2MHz 280 240 0.454MHz 200 160 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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33.3.2 I/O Pin Characteristics 33.3.2.1 Pull-up Figure 33-179. I/O pin pull-up resistor current vs. input voltage. VCC = 1.8V. 70 60 IPIN [µA] 50 40 30 20 -40°C 25°C 85°C 10 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VPIN [V] Figure 33-180. I/O pin pull-up resistor current vs. input voltage. VCC = 3.0V. 120 105 90 IPIN [µA] 75 60 45 30 -40°C 25°C 85°C 15 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.
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Figure 33-181. I/O pin pull-up resistor current vs. input voltage. VCC = 3.3V. 135 120 105 IPIN [µA] 90 75 60 45 30 -40°C 25°C 85°C 15 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 VPIN [V] 33.3.2.2 Output Voltage vs. Sink/Source Current Figure 33-182. I/O pin output voltage vs. source current. VCC = 1.8V. 1.9 1.7 VPIN [V] 1.5 1.3 1.1 -40°C 85°C 0.9 25°C 0.7 0.
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Figure 33-183. I/O pin output voltage vs. source current. VCC = 3.0V. 3.2 2.8 2.4 VPIN [V] 2 1.6 1.2 -40°C 25°C 0.8 85°C 0.4 0 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 -12 -9 -6 -3 0 IPIN [mA] Figure 33-184. I/O pin output voltage vs. source current. VCC = 3.3V. 3.6 3.2 2.8 VPIN [V] 2.4 2.0 1.6 -40°C 1.2 0.8 25°C 85°C 0.4 0.
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Figure 33-185. I/O pin output voltage vs. source current. 3.7 3.6 V 3.3 V 3.3 3.0 V 2.9 VPIN [V] 2.7 V 2.5 2.1 1.8 V 1.6 V 1.7 1.3 0.9 0.5 -24 -21 -18 -15 -12 -9 -6 -3 0 IPIN [mA] Figure 33-186. I/O pin output voltage vs. sink current. VCC = 1.8V. 1.0 25°C 0.9 0.8 85°C VPIN [V] 0.7 0.6 -40°C 0.5 0.4 0.3 0.2 0.1 0.
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Figure 33-187. I/O pin output voltage vs. sink current. VCC = 3.0V. 1.0 85°C 0.9 25°C 0.8 -40°C VPIN [V] 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 3 6 9 12 15 18 21 24 27 30 IPIN [mA] Figure 33-188. I/O pin output voltage vs. sink current. VCC = 3.3V. VPIN [V] 1.0 0.9 85°C 0.8 25°C 0.7 -40°C 0.6 0.5 0.4 0.3 0.2 0.1 0.
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Figure 33-189. I/O pin output voltage vs. sink current. 1.50 1.6 V 1.35 1.8 V 1.20 VPIN [V] 1.05 2.7 V 3.0 V 3.3 V 3.6 V 0.90 0.75 0.60 0.45 0.30 0.15 0.00 0 3 6 9 12 15 18 21 24 27 30 IPIN [mA] 33.3.2.3 Thresholds and Hysteresis Figure 33-190. I/O pin input threshold voltage vs. VCC. T = 25°C. 1.8 VIH 1.6 VIL Vthreshold [V] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-191. I/O pin input threshold voltage vs. VCC. VIH I/O pin read as “1”. 1.8 -40 °C 25 °C 85 °C 1.7 Vthreshold [V] 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] Figure 33-192. I/O pin input threshold voltage vs. VCC. VIL I/O pin read as “0”. 1.75 -40 °C 25 °C 85 °C 1.60 Vthreshold [V] 1.45 1.30 1.15 1.00 0.85 0.70 0.55 0.40 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-193. I/O pin input hysteresis vs. VCC. 0.41 0.39 -40°C Vhysteresis [V] 0.37 0.35 0.33 0.31 25°C 0.29 0.27 0.25 85°C 0.23 0.21 0.19 0.17 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 2.2 2.4 2.6 2.8 3.0 Vcc [V] 33.3.3 ADC Characteristics Figure 33-194. INL error vs. external VREF. T = 25C, VCC = 3.6V, external reference. 2.7 2.4 Single-ended unsigned mode 2.1 INL [LSB] 1.8 1.5 1.2 Dif f erential mode 0.9 0.6 0.3 Single-ended signed mode 0.0 1.0 1.2 1.4 1.6 1.8 2.
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Figure 33-195. INL error vs. sample rate. T = 25C, VCC = 2.7V, VREF = 1.0V external. 1.6 1.4 Single-ended signed mode 1.2 INL [LSB] 1.0 0.8 Dif f erential mode 0.6 Single-ended signed mode 0.4 0.2 0.0 500 650 800 950 1100 1250 1400 1550 1700 1850 2000 ADC sample rate [kSps] Figure 33-196. INL error vs. input code 2.0 1.5 1.0 INL [LSB] 0.5 0.0 -0.5 -1.0 -1.5 -2.
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Figure 33-197. DNL error vs. external VREF. T = 25C, VCC = 3.6V, external reference. 1.1 1.0 Single-ended unsigned mode 0.9 DNL [LSB] 0.8 0.7 0.6 Dif f erential mode 0.5 0.4 Single-ended signed mode 0.3 0.2 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 Vref [V] Figure 33-198. DNL error vs. sample rate. T = 25C, VCC = 2.7V, VREF = 1.0V external. 0.43 0.41 Single-ended unsigned mode 0.38 DNL [LSB] 0.36 Dif f erential mode 0.33 0.31 0.28 0.26 Single-ended signed mode 0.
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Figure 33-199. DNL error vs. input code. 1.0 0.8 0.6 0.4 DNL [LSB] 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code Figure 33-200. Gain error vs. VREF. T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps. 12 Gain Error [mV] 10 Single-ended signed mode 8 Single-ended unsigned mode 6 4 2 Dif f erential mode 0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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Figure 33-201. Gain error vs. VCC. T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps. 7 6 Single-ended signed mode Gain Error [mV] 5 4 Single-ended unsigned mode 3 2 Dif f erential mode 1 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.6 2.8 3.0 Vcc [V] Figure 33-202. Offset error vs. VREF. T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps. -1.0 -1.1 -1.1 Offset Error [mV] -1.2 -1.2 Dif f erential mode -1.3 -1.3 -1.4 -1.4 -1.5 -1.5 1.0 1.2 1.4 1.6 1.8 2.0 2.
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Figure 33-203. Gain error vs. temperature. VCC = 2.7V, VREF = external 1.0V. 7 6 Single-ended signed mode Gain Error [mV] 5 4 Single-ended unsigned mode 3 2 Dif f erential mode 1 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [o C] Figure 33-204. Offset error vs. VCC. T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps. -0.3 -0.4 Offset Error [mV] -0.5 Dif f erential mode -0.6 -0.7 -0.8 -0.9 -1.0 -1.1 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-205. Noise vs. VREF. T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps. 0.9 Single-ended signed mode 0.8 Noise [mV RMS] 0.7 0.6 Single-ended unsigend mode 0.5 0.4 0.3 Dif f erential mode 0.2 0.1 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 Vref [V] Figure 33-206. Noise vs. VCC. T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps. 0.8 Single-ended signed mode 0.7 Noise [mV RMS] 0.6 0.5 Single-ended unsigned mode 0.4 0.
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33.3.4 Analog Comparator Characteristics Figure 33-207. Analog comparator hysteresis vs. VCC. High-speed, small hysteresis. 24 23 85°C 22 25°C VHYST [mV] 21 20 19 -40°C 18 17 16 15 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-208. Analog comparator hysteresis vs. VCC. Low power, small hysteresis. 36 85°C 34 VHYST [mV] 32 30 25°C 28 -40°C 26 24 22 20 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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Figure 33-209. Analog comparator hysteresis vs. VCC. High-speed mode, large hysteresis. 45 85°C 43 25°C 41 VHYST [mV] 39 -40°C 37 35 33 31 29 27 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-210. Analog comparator hysteresis vs. VCC. Low power, large hysteresis. 73 85°C 70 67 VHYST [mV] 64 25°C 61 58 -40°C 55 52 49 46 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-211. Analog comparator current source vs. calibration value. Temperature = 25°C. 8 ICURRENTSOURCE [µA] 7 6 5 3.6V 3.0V 2.7V 2.2V 1.8V 1.6V 4 3 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRCALIBA[3..0] Figure 33-212. Analog comparator current source vs. calibration value. VCC = 3.0V. 7.2 6.8 ICURRENTSOURCE [µA] 6.4 6.0 5.6 5.2 4.8 4.4 -40°C 25°C 85°C 4.0 3.6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRCALIBA[3..
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Figure 33-213. Voltage scaler INL vs. SCALEFAC. T = 25C, VCC = 3.0V. 0.15 0.12 0.09 INL [LSB] 0.06 0.03 0.00 -0.03 -0.06 -0.09 -0.12 -0.15 0 8 16 24 32 40 48 56 64 SCALEFAC 33.3.5 Internal 1.0V reference Characteristics Figure 33-214. ADC Internal 1.0V reference vs. temperature. 1.001 1.8 V 2.7 V 3.3 V 3.0 V 1.000 Bandgap Voltage [V] 0.999 0.998 0.997 0.996 0.995 0.994 0.993 0.
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33.3.6 BOD Characteristics Figure 33-215. BOD thresholds vs. temperature. BOD level = 1.6V. 1.641 Rising Vcc 1.638 1.635 VBOT [V] 1.632 1.629 Falling Vcc 1.626 1.623 1.620 1.617 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-216. BOD thresholds vs. temperature. BOD level = 3.0V. 3.07 Rising Vcc 3.06 VBOT [V] 3.05 3.04 3.03 Falling Vcc 3.02 3.01 3.
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33.3.7 External Reset Characteristics Figure 33-217. Minimum Reset pin pulse width vs. VCC. 130 125 120 tRST [ns] 115 110 105 100 95 -40°C 25°C 85°C 90 85 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-218. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 80 70 IRESET [µA] 60 50 40 30 20 -40°C 25°C 85°C 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
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Figure 33-219. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 135 120 105 IRESET [µA] 90 75 60 45 30 -40°C 25°C 85°C 15 0 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 VRESET [V] Figure 33-220. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 150 135 120 IRESET [µA] 105 90 75 60 45 30 -40°C 25°C 85°C 15 0 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.
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Figure 33-221. Reset pin input threshold voltage vs. VCC. VIH - Reset pin read as “1”. 2.2 -40°C 25°C 85°C 2.1 VTHRESHOLD [V] 1.9 1.8 1.6 1.5 1.3 1.2 1.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-222. Reset pin input threshold voltage vs. VCC. VIL - Reset pin read as “0”. 1.75 -40°C 25°C 85°C 1.60 1.45 VTHRESHOLD [V] 1.30 1.15 1.00 0.85 0.70 0.55 0.40 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
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33.3.8 Power-on Reset Characteristics Figure 33-223. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in continuous mode. 300 85°C 25°C -40°C 250 ICC [µA] 200 150 100 50 0 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 VCC [V] Figure 33-224. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in sampled mode. 200 180 85°C 25°C -40°C 160 140 ICC [µA] 120 100 80 60 40 20 0 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.
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33.3.9 Oscillator Characteristics 33.3.9.1 Ultra Low-Power internal oscillator Figure 33-225. Ultra Low-Power internal oscillator frequency vs. temperature. 34.1 33.8 Frequency [kHz] 33.5 33.2 32.9 3.6V 3.0V 2.7V 2.2V 1.8V 1.6V 32.6 32.3 32.0 31.7 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] 33.3.9.2 32.768kHz Internal Oscillator Figure 33-226. 32.768kHz internal oscillator frequency vs. temperature. 32.85 3.6V 3.0V 2.7V 2.2V 1.8V 1.6V 32.82 Frequency [kHz] 32.
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Figure 33-227. 32.768kHz internal oscillator frequency vs. calibration value. VCC = 3.0V, T = 25°C. 53 50 Frequency [kHz] 47 44 41 38 35 32 29 26 23 0 30 60 90 120 150 180 210 240 270 RC32KCAL[7..0] 33.3.9.3 2MHz Internal Oscillator Figure 33-228. 2MHz internal oscillator frequency vs. temperature. DFLL disabled. 2.12 2.10 Frequency [MHz] 2.08 2.06 2.04 3.6V 3.0V 2.7V 2.2V 1.8V 1.6V 2.02 2.00 1.98 1.
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Figure 33-229. 2MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz , internal oscillator . 2.010 1.6V 1.8V 2.7V 3.0V 2.2V 3.6V 2.007 Frequency [MHz] 2.004 2.001 1.998 1.995 1.992 1.989 1.986 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-230. 2MHz internal oscillator CALA calibration step size. VCC = 3V. Frequency Step size [%] 0.30 % 0.25 % 0.20 % -40°C 25°C 85°C 0.15 % 0.10 % 0.05 % 0.
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33.3.9.4 32MHz Internal Oscillator Figure 33-231. 32MHz internal oscillator frequency vs. temperature. DFLL disabled. 35.5 35.0 Frequency [MHz] 34.5 34.0 33.5 33.0 3.6V 3.0V 2.7V 2.2V 1.8V 1.6V 32.5 32.0 31.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-232. 32MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.10 3.6V 3.0V 2.7V 2.2V 1.8V 1.6V 32.07 Frequency [MHz] 32.04 32.01 31.98 31.95 31.92 31.
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Figure 33-233. 32MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.33 % Frequency Step size[%] 0.30 % 0.28 % -40°C 0.25 % 0.23 % 0.20 % 0.18 % 85°C 0.15 % 25°C 0.13 % 0.10 % 0 15 30 45 60 75 90 105 120 135 CALA Figure 33-234. 32MHz internal oscillator CALB calibration step size. VCC = 3.0V 2.80 % Frequency Step size [%] 2.60 % 2.40 % 2.20 % 2.00 % 1.80 % 1.60 % 1.40 % 1.20 % -40°C 25°C 85°C 1.00 % 0.
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33.3.9.5 32MHz internal oscillator calibrated to 48MHz Figure 33-235. 48MHz internal oscillator frequency vs. temperature. DFLL disabled. 53.4 52.6 Frequency[MHz] 51.8 51.0 50.2 3.6V 3.0V 2.7V 2.2V 1.8V 1.6V 49.4 48.6 47.8 47.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-236. 48MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 48.15 3.6V 3.0V 2.7V 2.2V 1.8V 1.6V 48.10 Frequency[MHz] 48.05 48.00 47.95 47.
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Figure 33-237. 48MHz internal oscillator CALA calibration step size. VCC = 3.0V 0.30 % Frequency Step size [%] 0.28 % 0.26 % 0.24 % 0.22 % -40°C 0.20 % 0.18 % 0.16 % 25°C 0.14 % 85°C 0.12 % 0.10 % 0 16 32 48 64 80 96 112 128 CALA 33.3.10 Two-Wire Interface characteristics Figure 33-238. SDA hold time vs. temperature.
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Figure 33-239. SDA hold time vs. supply voltage. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 2.8 3 3.4 3.5 3.6 VCC [V] 33.3.11 PDI characteristics Figure 33-240. Maximum PDI frequency vs. VCC. 33 Frequency max [MHz] 30 28 25 23 -40°C 25°C 85°C 20 18 15 13 10 1.6 1.8 2 2.2 2.4 2.6 3.2 3.4 3.
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33.4 ATxmega128D4 33.4.1 Current consumption 33.4.1.1 Active mode supply current Figure 33-241. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 800 3.6V 700 600 Icc [µA] 3.0V 500 2.7V 400 2.2V 300 1.8V 1.6V 200 100 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 33-242. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 13.5 12.0 3.6V Icc [mA] 10.5 3.0V 9.0 2.7V 7.5 6.0 4.5 2.2V 3.0 1.8V 1.
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Figure 33-243. Active mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 270 -40°C 240 25°C Icc [µA] 210 85°C 180 150 120 90 60 30 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-244. Active mode supply current vs. VCC. fSYS = 1MHz external clock. 800 -40°C 25°C 85°C 700 Icc [µA] 600 500 400 300 200 100 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-245. Active mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 1400 -40°C 25°C 85°C 1225 Icc [µA] 1050 875 700 525 350 175 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] Figure 33-246. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 5.8 -40°C 25°C 85°C 5.2 Icc [mA] 4.6 4.0 3.4 2.8 2.2 1.6 1.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-247. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator. 13.4 12.6 -40°C 25°C 85°C Icc [mA] 11.8 11.0 10.2 9.4 8.6 7.8 7.0 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 33.4.1.2 Idle mode supply current Figure 33-248. Idle mode supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 160 3.6 V Icc [µA] 140 120 3.0 V 100 2.7 V 80 2.2 V 60 1.8 V 1.6 V 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
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Figure 33-249. Idle mode supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 5.4 3.6V 4.8 Icc [mA] 4.2 3.0V 3.6 2.7V 3.0 2.4 1.8 2.2V 1.2 1.8V 0.6 0 0 4 8 12 16 20 24 28 32 Frenquecy [MHz] Figure 33-250. Idle mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 36 35 -40°C 34 Icc [µA] 85°C 33 25°C 32 31 30 29 28 27 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-251. Idle mode supply current vs. VCC. fSYS = 1MHz external clock. 160 85°C 25°C -40°C 150 140 Icc [µA] 130 120 110 100 90 80 70 60 50 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] Figure 33-252. Idle mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 310 -40°C 25°C 85°C 290 270 Icc [µA] 250 230 210 190 170 150 130 110 90 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-253. Idle mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 2.0 -40 °C 25 °C 85 °C 1.8 Icc [mA] 1.6 1.4 1.2 1.0 0.8 0.6 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] Figure 33-254. Idle mode current vs. VCC. fSYS = 32MHz internal oscillator. 5.00 -40°C 25°C 85°C 4.75 Icc [mA] 4.50 4.25 4.00 3.75 3.50 3.25 3.00 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.
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33.4.1.3 Power-down mode supply current Figure 33-255. Power-down mode supply current vs. temperature. All functions disabled. 1.8 3.6V 1.6 3.0V 2.7V 2.2V 1.8V 1.6V 1.4 Icc [µA] 1.2 1 0.8 0.6 0.4 0.2 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-256. Power-down mode supply current vs. VCC. All functions disabled. 1.8 85°C 1.6 1.4 Icc [µA] 1.2 1 0.8 0.6 0.4 0.2 25°C -40°C 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-257. Power-down mode supply current vs. VCC. Watchdog and sampled BOD enabled. 3.2 3.0 85°C 2.8 Icc [µA] 2.6 2.4 2.2 2.0 1.8 1.6 25°C -40°C 1.4 1.2 1.0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] 33.4.1.4 Power-save mode supply current Figure 33-258. Power-save mode supply current vs.VCC. Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC. 0.9 Normal mode 0.8 0.7 ICC [µA] 0.6 Low-power mode 0.5 0.4 0.3 0.2 0.1 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
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33.4.1.5 Standby mode supply current Figure 33-259. Standby supply current vs. VCC. Standby, fSYS = 1MHz. 9.5 85°C 9.0 8.5 25°C -40°C 8.0 ICC [µA] 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC[V] Figure 33-260. Standby supply current vs. VCC. 25°C, running from different crystal oscillators. 480 16MHz 12MHz 440 ICC [µA] 400 360 320 8MHz 2MHz 280 240 0.454MHz 200 160 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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33.4.2 I/O Pin Characteristics 33.4.2.1 Pull-up Figure 33-261. I/O pin pull-up resistor current vs. input voltage. VCC = 1.8V. 72 64 56 I [µA] 48 40 32 24 16 -40°C 25°C 85°C 8 0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 VPIN [V] Figure 33-262. I/O pin pull-up resistor current vs. input voltage. VCC = 3.0V. 120 105 I [µA] 90 75 60 45 30 85°C 25°C -40°C 15 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.
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Figure 33-263. I/O pin pull-up resistor current vs. input voltage. VCC = 3.3V. 135 120 105 I [µA] 90 75 60 45 30 85 °C 25 °C -40 °C 15 0 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 3.4 -2 -1 0 VPIN [V] 33.4.2.2 Output Voltage vs. Sink/Source Current VPIN [V] Figure 33-264. I/O pin output voltage vs. source current. VCC = 1.8V. 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.
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Figure 33-265. I/O pin output voltage vs. source current. VCC = 3.0V. 3.3 2.95 2.6 VPIN [V] 2.25 1.9 1.55 -40°C 1.2 25°C 85°C 0.85 0.5 -30 -27 -24 -21 -18 -15 -12 -9 -6 -12 -9 -6 -3 0 IPIN [mA] Figure 33-266. I/O pin output voltage vs. source current. VCC = 3.3V. 3.5 3.2 2.9 VPIN [V] 2.6 2.3 2 -40°C 1.7 1.4 85°C 25°C 1.1 0.8 0.
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Figure 33-267. I/O pin output voltage vs. source current. 3.65 3.6V 3.3 3.3V 2.95 3.0V 2.7V VPIN [V] 2.6 2.25 1.9 1.8V 1.6V 1.55 1.2 0.85 0.5 -24 -21 -18 -15 -12 -9 -6 -3 85°C 25°C 0 IPIN [mA] Figure 33-268. I/O pin output voltage vs. sink current. VCC = 1.8V. 1 0.9 -40°C 0.8 VPIN[V] 0.7 0.6 0.5 0.4 0.3 0.2 0.
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Figure 33-269. I/O pin output voltage vs. sink current. VCC = 3.0V. 1.1 1 85°C 0.9 25°C VPIN [V] 0.8 -40°C 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 3 6 9 12 15 18 21 24 27 30 IPIN [mA] Figure 33-270. I/O pin output voltage vs. sink current. VCC = 3.3V. 1.0 85°C 0.9 25°C 0.8 -40°C VPIN[V] 0.7 0.6 0.5 0.4 0.3 0.2 0.
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Figure 33-271. I/O pin output voltage vs. sink current. 1.5 1.8V 1.6V 1.35 1.2 2.7V 3.0V 3.3V 3.6V VPIN [V] 1.05 0.9 0.75 0.6 0.45 0.3 0.15 0 0 3 6 9 12 15 18 21 24 27 30 IPIN [mA] 33.4.2.3 Thresholds and Hysteresis Figure 33-272. I/O pin input threshold voltage vs. VCC. T = 25°C. 1.8 VIH 1.6 VIL Vthreshold [V] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-273. I/O pin input threshold voltage vs. VCC. VIH I/O pin read as “1”. 1.8 -40 °C 25 °C 85 °C 1.7 Vthreshold [V] 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] Figure 33-274. I/O pin input threshold voltage vs. VCC. VIL I/O pin read as “0”. 1.75 -40 °C 25 °C 85 °C 1.60 Vthreshold [V] 1.45 1.30 1.15 1.00 0.85 0.70 0.55 0.40 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-275. I/O pin input hysteresis vs. VCC. 0.41 0.39 -40°C 0.37 Vthreshold [V] 0.35 0.33 0.31 25°C 0.29 0.27 0.25 85°C 0.23 0.21 0.19 0.17 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] 33.4.3 ADC Characteristics Figure 33-276. INL error vs. external VREF. T = 25C, VCC = 3.6V, external reference. 1.8 1.7 1.6 Differential Signed INL [LSB] 1.5 Single-ended Unsigned 1.4 1.3 1.2 1.1 1 0.9 Single-ended Signed 0.8 0.7 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.
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Figure 33-277. INL error vs. sample rate. T = 25C, VCC = 3.6V, VREF = 3.0V external. 1.4 1.35 1.3 Differential Mode INL [LSB] 1.25 1.2 Single-ended Unsigned 1.15 1.1 1.05 Single-ended Signed 1 0.95 0.9 500 650 800 950 1100 1250 1400 1550 1700 1850 2000 ADC Sample Rate [kSPS] Figure 33-278. INL error vs. input code 2.0 1.5 INL [LSB] 1.0 0.5 0 -0.5 -1.0 -1.5 -2.
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Figure 33-279. DNL error vs. external VREF. T = 25C, VCC = 3.6V, external reference. 0.9 0.88 0.86 DNL [LSB] Differential Mode 0.84 Single-ended Signed 0.82 0.8 0.78 Single-ended Unsigned 0.76 0.74 0.72 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 VREF [V] Figure 33-280. DNL error vs. sample rate. T = 25C, VCC = 3.6V, VREF = 3.0V external. 0.9 0.89 Differential Signed 0.88 DNL [LSB] 0.87 0.86 0.85 Single-ended Signed 0.84 0.83 0.82 0.81 Single-ended Unsigned 0.8 0.
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Figure 33-281. DNL error vs. input code. 0.8 0.6 DNL [LSB] 0.4 0.2 0 -0.2 -0.4 -0.6 0 512 1024 1536 2048 2560 3072 3584 4096 ADC Input Code Figure 33-282. Gain error vs. VREF. T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps. 3 Single-ended Signed Gain Error [mV] 2 1 Differential Mode 0 -1 Single-ended Unsigned -2 -3 -4 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.
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Figure 33-283. Gain error vs. VCC. T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps. 2.2 1.9 Single-ended Signed Gain Error [mV] 1.6 1.3 Differential Mode 1 0.7 0.4 Single-ended Unsigned 0.1 -0.2 -0.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-284. Offset error vs. VREF. T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps. -1 Offset Error [mV] -1.1 -1.2 -1.3 -1.4 -1.5 Differential Mode -1.6 -1.7 -1.8 -1.9 -2 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.
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Figure 33-285. Gain error vs. temperature. VCC = 3.0V, VREF = external 2.0V. 3 2 Gain Error [mV] Single-ended Signed 1 Differential Signed 0 -1 Single-ended Unsigned -2 -3 -4 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [ºC] Figure 33-286. Offset error vs. VCC. T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps. -0.3 -0.4 Offset Error [mV] -0.5 -0.6 -0.7 Differential Signed -0.8 -0.9 -1 -1.1 -1.2 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-287. Noise vs. VREF. T = 25C, VCC = 3.6V, ADC sampling speed = 500ksps. 1.3 Single-ended Signed Noise [mV RMS] 1.15 Single-ended Unsigned 1 0.85 0.7 0.55 Differential Signed 0.4 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 VREF [V] Figure 33-288. Noise vs. VCC. T = 25C, VREF = external 1.0V, ADC sampling speed = 500ksps. 1.3 1.2 Single-ended Signed Noise [mV RMS] 1.1 1 0.9 0.8 Single-ended Unsigned 0.7 0.6 0.5 Differential Signed 0.4 0.3 1.6 1.8 2 2.2 2.4 2.6 2.
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33.4.4 Analog Comparator Characteristics Figure 33-289. Analog comparator hysteresis vs. VCC. High-speed, small hysteresis. 13 12 85°C VHYST [mV] 11 10 25°C 9 8 7 -40°C 6 5 4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-290. Analog comparator hysteresis vs. VCC. Low power, small hysteresis. 27 85°C 26 25 VHYST [mV] 24 25°C 23 22 21 -40°C 20 19 18 17 16 15 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-291. Analog comparator hysteresis vs. VCC. High-speed mode, large hysteresis. 32 30 85°C VHYST [mV] 28 26 25°C 24 22 -40°C 20 18 16 14 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-292. Analog comparator hysteresis vs. VCC. Low power, large hysteresis. 68 64 85°C VHYST [mV] 60 56 25°C 52 48 -40°C 44 40 36 32 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Figure 33-293. Analog comparator current source vs. calibration value. Temperature = 25°C. 8 7.5 ICURRENTSOURCE [µA] 7 6.5 6 5.5 5 4.5 3.6V 4 3.0V 3.5 3 2.2V 1.8V 2.5 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRCALIBA[3..0] Figure 33-294. Analog comparator current source vs. calibration value. VCC = 3.0V. 7 ICURRENTSOURCE [µA] 6.5 6 5.5 5 4.5 -40°C 25°C 85°C 4 3.5 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRCALIBA[3..
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Figure 33-295. Voltage scaler INL vs. SCALEFAC. T = 25C, VCC = 3.0V. 0.050 0.025 INL [LSB] 0 -0.025 -0.050 -0.075 -0.100 25°C -0.125 -0.150 0 10 20 30 40 50 60 70 SCALEFAC 33.4.5 Internal 1.0V reference Characteristics Figure 33-296. ADC Internal 1.0V reference vs. temperature. 1.0024 1.6V Bandgap Voltage [V] 1.002 1.8V 1.0016 1.0012 1.0008 1.0004 2.7V 1 0.9996 3.0V 3.6V 0.9992 0.9988 0.
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33.4.6 BOD Characteristics Figure 33-297. BOD thresholds vs. temperature. BOD level = 1.6V. 1.608 1.605 Rising Vcc 1.602 VBOT [V] 1.599 1.596 Falling Vcc 1.593 1.59 1.587 1.584 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 55 65 75 85 Temperature [°C] Figure 33-298. BOD thresholds vs. temperature. BOD level = 3.0V. 3.03 3.02 Rising Vcc 3.01 VBOT [V] 3 2.99 2.98 Falling Vcc 2.97 2.96 2.95 2.
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33.4.7 External Reset Characteristics Figure 33-299. Minimum Reset pin pulse width vs. VCC. 130 125 120 TRST [ns] 115 110 105 100 85°C 95 90 25°C -40°C 85 80 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] Figure 33-300. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 80 72 64 IRESET [µA] 56 48 40 32 24 16 -40°C 25°C 85°C 8 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
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Figure 33-301. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 135 120 105 IRESET [µA] 90 75 60 45 30 -40°C 25°C 85°C 15 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 VRESET [V] Figure 33-302. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 150 135 120 IRESET [µA] 105 90 75 60 45 30 -40°C 25°C 85°C 15 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.
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Figure 33-303. Reset pin input threshold voltage vs. VCC. VIH - Reset pin read as “1”. 1.8 -40°C 25°C 85°C 1.6 VTHRESHOLD [V] 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-304. Reset pin input threshold voltage vs. VCC. VIL - Reset pin read as “0”. 1.8 -40°C 25°C 85°C 1.6 VTHRESHOLD [V] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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33.4.8 Power-on Reset Characteristics Figure 33-305. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in continuous mode. 700 -40 °C 600 25 °C 85 °C I CC [uA] 500 400 300 200 100 0 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 VCC [V] Figure 33-306. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in sampled mode. 650 -40 °C 585 520 25 °C 455 85 °C I CC [µA] 390 325 260 195 130 65 0 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.
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33.4.9 Oscillator Characteristics 33.4.9.1 Ultra Low-Power internal oscillator Figure 33-307. Ultra Low-Power internal oscillator frequency vs. temperature. 33.75 33.50 Frequency [kHz] 33.25 33.00 32.75 32.50 3.6V 3.3V 3.0V 32.25 32.00 2.7V 1.8V 1.6V 31.75 31.50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [°C] 33.4.9.2 32.768kHz Internal Oscillator Figure 33-308. 32.768kHz internal oscillator frequency vs. temperature. 32.76 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 32.
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Figure 33-309. 32.768kHz internal oscillator frequency vs. calibration value. VCC = 3.0V, T = 25°C. 52 3.0 V Frequency [kHz] 49 46 43 40 37 34 31 28 25 22 0 24 48 72 96 120 144 168 192 216 240 264 RC32KCAL[7..0] 33.4.9.3 2MHz Internal Oscillator Figure 33-310. 2MHz internal oscillator frequency vs. temperature. DFLL disabled. 2.16 Frequency [MHz] 2.14 2.12 2.10 2.08 2.06 2.04 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 2.02 2.00 1.
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Figure 33-311. 2MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 2.002 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 2 Frequency [MHz] 1.998 1.996 1.994 1.992 1.99 1.988 1.986 1.984 1.982 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [°C] Figure 33-312. 2MHz internal oscillator CALA calibration step size. VCC = 3V. 0.3 0.28 Step Size [%] 0.26 0.24 0.22 0.2 -40°C 0.18 25°C 0.16 85°C 0.
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33.4.9.4 32MHz Internal Oscillator Figure 33-313. 32MHz internal oscillator frequency vs. temperature. DFLL disabled. 36 35.55 Frequency [MHz] 35.1 34.65 34.2 33.75 33.3 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 32.85 32.4 31.95 31.5 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [°C] Figure 33-314. 32MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.01 1.8V 2.2V 2.7V 3.0V 3.3V 3.6V 31.98 Frequency [MHz] 31.95 31.92 31.89 31.86 31.
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Figure 33-315. 32MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.7 0.63 Step Size [%] 0.56 0.49 0.42 0.35 0.28 -40°C 85°C 25°C 0.21 0.14 0.07 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 CALA 33.4.9.5 32MHz internal oscillator calibrated to 48MHz Figure 33-316. 48MHz internal oscillator frequency vs. temperature. DFLL disabled. 53.9 53.2 Frequency [MHz] 52.5 51.8 51.1 50.4 49.7 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 49 48.3 47.6 46.
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Figure 33-317. 48MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 3.6V 3.3V 3.0V 2.7V 2.2V 1.8V 48 Frequency [MHz] 47.95 47.9 47.85 47.8 47.75 47.7 47.65 47.6 47.55 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [°C] 33.4.10 Two-Wire Interface characteristics Figure 33-318. SDA hold time vs. temperature.
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Figure 33-319. SDA hold time vs. supply voltage. 500 450 3 Hold time [ns] 400 350 2 300 250 200 150 100 1 50 0 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 2.8 3 3.4 3.5 3.6 VCC [V] 33.4.11 PDI characteristics Figure 33-320. Maximum PDI frequency vs. VCC. 33 Frequency max [MHz] 30 28 25 23 -40°C 25°C 85°C 20 18 15 13 10 1.6 1.8 2 2.2 2.4 2.6 3.2 3.4 3.
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34. Errata 34.1 ATxmega16D4 / ATxmega32D4 34.1.1 Rev. I  Temperature sensor not calibrated 1. Temperature sensor not calibrated Temperature sensor factory calibration not implemented. Problem fix/Workaround None. 34.1.2 Rev. F/G/H Not sampled. 34.1.3 Rev.
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Problem fix/Workaround For CWCM no workaround is required. For PGM in latched mode, disable the DTI channels before returning from the fault condition. Then, set correct OUTOVEN value and enable the DTI channels, before the direction (DIR) register is written to enable the correct outputs again. For PGM in cycle-by-cycle mode there is no workaround. 4.
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34.1.5 Rev. A/B  Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously  VCC voltage scaler for AC is non-linear  ADC gain stage cannot be used for single conversion  ADC has increased INL error for some operating conditions  ADC gain stage output range is limited to 2.4 V  ADC Event on compare match non-functional  ADC propagation delay is not correct when 8x -64x gain is used  Bandgap measurement with the ADC is non-functional when VCC is below 2.
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1. Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input for another AC, the first comparator will be affected for up to 1 ìs and could potentially give a wrong comparison result. Problem fix/Workaround If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling any of them. 2.
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1x gain: 2.4V 2x gain: 1.2V 4x gain: 0.6v 8x gain: 300mV 16x gain: 150mV 32x gain: 75mV 64x gain: 38mV Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or keep ADC voltage reference below 2.4V. 6. ADC Event on compare match non-functional ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE.
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Problem fix/Workaround Table 34-1. Configure PWM and CWCM according to this table. PGM CWCM Description 0 0 PGM and CWCM disabled 0 1 PGM enabled 1 0 PGM and CWCM enabled 1 1 PGM enabled 11 PWM is not restarted properly after a fault in cycle-by-cycle mode When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present.
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Problem fix/Workaround None for Output/Pull configuration. For inverted I/O, configure the Analog Comparator to give an inverted result (i.e. connect positive input to the negative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator output. 17.
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23. Clearing TWI Stop Interrupt Flag may lock the bus If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets this flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will lock the bus. Problem fix/Workaround Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for the SCL pin to be low before clearing APIF.
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Problem fix/Workaround Configure the analog comparator setup to give an inverted result, or use an external inverter to change polarity of Analog Comparator Output. 28. Non available functions and options The below function and options are not available. Writing to any registers or fuse to try and enable or configure these functions or options will have no effect, and will be as writing to a reserved address location. ● TWIE, the TWI module on PORTE.
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34.2 ATxmega64D4 34.2.1 Rev. D  Temperature sensor not calibrated 1. Temperature sensor not calibrated Temperature sensor factory calibration not implemented. Problem fix/Workaround None. 34.2.2 Rev. B/C Not sampled. 34.2.3 Rev. A  ADC may have missing codes in SE unsigned mode at low temp and low VCC  Temperature sensor not calibrated 1.
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35. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 35.1 8135P – 01/2014 1. 35.2 Updated the typical characteristics of “ATxmega16D4” and “ATxmega32D4” with characterizations at 105C 8135O – 08/2013 1. Updated “Errata” : ● ATxmega16D4/32D4: Added Temperature sensor not calibrated to “Rev. I” , “Rev. E” and “Rev. A/B” ● ● 35.
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35.5 35.6 8135L – 08/2012 1. Editing updates. 2. Updated all tables in the “Electrical Characteristics” on page 63. 3. Added new “Typical Characteristics” on page 143. 4. Added new Errata “Rev. E” on page 304. 5. Added new ERRATA on “Rev. A/B” on page 306: Non available functions and options 8135K – 06/2012 1. 35.7 35.8 8135J – 12/10 1. Datasheet status changed to complete: Preliminary removed from the front page. 2. Updated all tables in the “Electrical Characteristics” on page 63. 3.
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5. Added AVCC in ”ADC Characteristics” on page 62. 6. Updated Start up time in ”ADC Characteristics” on page 62. 7. Updated and fixed typo in “Errata” section. 35.11 8135F – 02/10 1. Added ”PDI Speed” on page 89. 35.12 8135E – 02/10 1. Updated the device pin-out Figure 2-1 on page 3. PDI_CLK and PDI_DATA renamed only PDI. 2. Updated Table 7-3 on page 18. No of Pages for ATxmega32D4: 32 3. Updated ”Alternate Port Functions” on page 29. 4.
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6. Updated ”Overview” on page 35. 7. Updated Table 27-5 on page 49. 8. Updated ”Peripheral Module Address Map” on page 50. 35.15 8135B – 09/09 1. Added ”Electrical Characteristics” on page 58. 2. Added ”Typical Characteristics” on page 67. 35.16 8135A – 03/09 1. Initial revision.
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XMEGA D4 [DATASHEET] 8135P–AVR–01/2014 318
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Pinout/Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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11. System Control and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11.1 11.2 11.3 11.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Sources . . . . . . . . . . . . . . . . . . . . .
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23. IRCOM – IR Communication Module . . . . . . . . . . . . . . . . . . . . . . . . 41 23.1 23.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 24. CRC – Cyclic Redundancy Check Generator . . . . . . . . . . . . . . . . . 42 24.1 24.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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35.4 35.5 35.6 35.7 35.8 35.9 35.10 35.11 35.12 35.13 35.14 35.15 35.16 8135M – 02/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8135L – 08/2012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8135K – 06/2012. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8135J – 12/10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Atmel Corporation 1600 Technology Drive Atmel Asia Limited Unit 01-5 & 16, 19F Atmel Munich GmbH Business Campus Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg San Jose, CA 95110 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku USA 418 Kwun Tong Roa D-85748 Garching b. Munich Tokyo 141-0032 Tel: (+1) (408) 441-0311 Kwun Tong, Kowloon GERMANY JAPAN Fax: (+1) (408) 487-2600 HONG KONG Tel: (+49) 89-31970-0 Tel: (+81) (3) 6417-0300 www.atmel.