Datasheet

175
XMEGA D3 [DATASHEET]
Atmel-8134N-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–03/2014
Figure 32-41. SPI timing requirements in slave mode.
Table 32-173. SPI timing characteristics and requirements.
MSB LSB
MSB LSB
t
SIS
t
SIH
t
SSCKW
t
SSCKW
t
SSCK
t
SSH
t
SOSSH
t
SCKR
t
SCKF
t
SOS
t
SSS
t
SOSSS
MISO
(Data output)
MOSI
(Data input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
Symbol Parameter Condition Min. Typ. Max. Units
t
SCK
SCK period Master
(See Table 20-3 in
XMEGA D manual)
ns
t
SCKW
SCK high/low width Master 0.5 * SCK
t
SCKR
SCK rise time Master 2.7
t
SCKF
SCK fall time Master 2.7
t
MIS
MISO setup to SCK Master 10
t
MIH
MISO hold after SCK Master 10
t
MOS
MOSI setup SCK Master 0.5 * SCK
t
MOH
MOSI hold after SCK Master 1
t
SSCK
Slave SCK Period Slave 4 * t Clk
PER
t
SSCKW
SCK high/low width Slave 2 * t Clk
PER
t
SSCKR
SCK rise time Slave 1600
t
SSCKF
SCK fall time Slave 1600
t
SIS
MOSI setup to SCK Slave 3
t
SIH
MOSI hold after SCK Slave tClk
PER
t
SSS
SS setup to SCK Slave 21
t
SSH
SS hold after SCK Slave 20
t
SOS
MISO setup SCK Slave 8
t
SOH
MISO hold after SCK Slave 13
t
SOSS
MISO setup after SS low Slave 11
t
SOSH
MISO hold after SS high Slave 8