Datasheet

6
XMEGA D3 [DATASHEET]
Atmel-8134N-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–03/2014
3.1 Block diagram
Figure 3-1. XMEGA D3 block diagram.
Power
Supervision
POR/BOD &
RESET
PORT A (8)
PORT B (8)
SRAMADCA
ACA
OCD
Int. Refs.
PDI
PA[0..7]
PB[0..7]
Watchdog
Timer
Watchdog
Oscillator
Interrupt
Controller
DATA BUS
Prog/Debug
Controller
VCC
GND
Oscillator
Circuits/
Clock
Generation
Oscillator
Control
Real Time
Counter
Event System
Controller
AREFA
AREFB
PDI_DATA
RESET/
PDI_CLK
Sleep
Controller
CRC
PORT C (8)
PC[0..7]
TCC0:1
USARTC0
TWIC
SPIC
PD[0..7] PE[0..7]
PORT D (8)
TCD0
USARTD0
SPID
TCE0
USARTE0
TWIE
PORT E (8)
Tempref
VCC/10
PORT R (2)
XTAL1
XTAL2
PR[0..1]
DATA BUS
NVM Controller
Flash EEPROM
IRCOM
BUS Matrix
CPU
TOSC1
TOSC2
TCF0 PF[0..7]
PORT F (8)
EVENT ROUTING NETWORK
To Clock
Generator
Digital function
Analog function / Oscillators
Programming, debug,
External clock / Crystal pins
General Purpose I /O
Ground
Power