Datasheet

369
XMEGA D3 [DATASHEET]
Atmel-8134N-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–03/2014
16. NMI Flag for Crystal Oscillator Failure automatically cleared
NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI
interrupt handler.
Problem fix/Workaround
This device revision has only one NMI interrupt source, so checking the interrupt source in software is not
required.
17. Writing EEPROM or Flash while reading any of them will not work
The EEPROM and Flash cannot be written while reading EEPROM or Flash, or while executing code in
Active mode.
Problem fix/Workaround
Enter IDLE sleep mode within 2.5µs (five 2MHz clock cycles and 80 32MHz clock cycles) after starting an
EEPROM or flash write operation. Wake-up source must either be EEPROM ready or NVM ready interrupt.
Alternatively set up a Timer/Counter to give an overflow interrupt 7ms after the erase or write operation has
started, or 13ms after atomic erase-and-write operation has started, and then enter IDLE sleep mode.
18. RTC Counter value not correctly read after sleep
If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC
PER as the device is entering sleep, the value in the RTC count register can not be read correctly within the
first prescaled RTC clock cycle after wakeup. The value read will be the same as the value in the register
when entering sleep.
The same applies if RTC Compare Match is used as wake-up source.
Problem fix/Workaround
Wait at least one prescaled RTC clock cycle before reading the RTC CNT value.
19. Pending asynchronous RTC-interrupts will not wake up device
Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed,
will be ignored until the device is woken from another source or the source triggers again.
Problem fix/Workaround
None.
20. TWI Transmit collision flag not cleared on repeated start
The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only
cleared on start.
Problem fix/Workaround
Clear the flag in software after address interrupt.
21. Clearing TWI Stop Interrupt Flag may lock the bus
If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets
this flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will
lock the bus.