Datasheet

164
XMEGA D3 [DATASHEET]
Atmel-8134N-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–03/2014
Table 32-154. Clock and timing.
V
in
Input range 0 V
REF
VConversion range Differential mode, Vinp - Vinn -V
REF
V
REF
Conversion range Single ended unsigned mode, Vinp -V V
REF
- V
V Fixed offset voltage 200 lsb
Symbol Parameter Condition Min. Typ. Max. Units
Clk
ADC
ADC clock frequency
Maximum is 1/4 of peripheral clock frequency 100 1800
kHz
Measuring internal signals 100 125
f
ClkADC
Sample rate 16 300
ksps
f
ADC
Sample rate
Current limitation (CURRLIMIT) off 16 300
CURRLIMIT = LOW 16 250
CURRLIMIT = MEDIUM 16 150
CURRLIMIT = HIGH 16 50
Sampling time
Configurable in steps of 1/2 Clk
ADC
cycles up
to 32 Clk
ADC
cycles
0.28 320 µs
Conversion time (latency)
(RES+1)/2 + GAIN
RES (Resolution) = 8 or 12, GAIN = 0 to 3
5.5 10
Clk
ADC
cyclesStart-up time ADC clock cycles 12 24
ADC settling time After changing reference or input mode 7 7
Symbol Parameter Condition Min. Typ. Max. Units