Datasheet

53
XMEGA B [DATASHEET]
8291B–AVR–01/2013
5.13 Register Description – DMA Controller
5.13.1 CTRL – Control register
 Bit 7 – ENABLE: Enable
Setting this bit enables the DMA controller. If the DMA controller is enabled and this bit is written to zero, the ENABLE bit
is not cleared before the internal transfer buffer is empty, and the DMA data transfer is aborted.
 Bit 6 – RESET: Software Reset
Writing a one to RESET will be ignored as long as DMA is enabled (ENABLE = 1). This bit can be set only when the DMA
controller is disabled (ENABLE = 0).
 Bit 5:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 2 – DBUFMODE: Double Buffer Mode
This bit enables the double buffer mode.
 Bit 1 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bits to zero when
this register is written.
 Bit 0 – PRIMODE: Channel Priority Mode
This bit determines the internal channel priority according to Table 5-1.
Table 5-1. Channel priority settings
5.13.2 INTFLAGS – Interrupt Status register
 Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
Bit 7654 3 2 10
+0x00 ENABLE RESET
– – – DBUFMODE – PRIMODE
Read/Write R/W R/W R R R R/W R R/W
Initial Value 0 0 0 0 0 0 0 0
PRIMODE Group Configuration Description
0 RR01 Round robin
1 CH01 Channel0 has priority
Bit 7654 3 2 1 0
+0x03
– – CH1ERRIF CH0ERRIF – – CH1TRNFIF CH0TRNFIF
Read/Write R R R/W R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0