Datasheet

4
XMEGA B [DATASHEET]
8291B–AVR–01/2013
Figure 2-1. Atmel AVR XMEGA B block diagram.
In Table 2-1 on page 5 a feature summary for the XMEGA B family is shown, split into one feature summary column for
each sub-family. Each sub-family has identical feature set, but different memory options, refer to their device datasheet
for ordering codes and memory options.
Power
Supervision
POR/BOD &
RESET
PORT A (8)
PORT B (8)
EVENT ROUTING NETWORK
DMA
Controller
BUS Matrix
SRAM
ADCA
ACA
ADCB
ACB
OCD
PORT M (8)
PDI
SEG[31..24] /
PM[0..7]
SEG[0..23]
COM[0..3]
PA[0..7]
PB[0..7]/
JTAG
Watchdog
Timer
Watchdog
Oscillator
Interrupt
Controller
DATA BUS
Prog/Debug
Controller
VCC
GND
PORT R (2)
PR[0..1]
Oscillator
Control
Real Time
Counter
Event System
Controller
JTAG
PDI_DATA
RESET /
PDI_CLK
PORT B
Sleep
Controller
DES
CRC
IRCOM
PORT G (8)
SEG[39..32] /
PG[0..7]
LCD POWER[0..4]
PORT C (8)
PC[0..7]
TCC0:1
USARTC0
TWIC
SPIC
PD[0..2] PE[0..7]
PORT D (3)
TCE0
USARTE0
PORT E (8)
USB
EVENT ROUTING NETWORK
AES
Int. Refs.
AREFA
AREFB
Tempref
VCC/10
CPU
NVM Controller
Flash EEPROM
DATA BUS
LCD
TOSC1
TOSC2
To Clock
Generator
XTAL2 /
TOSC2
XTAL1 /
TOSC1
Oscillator
Circuits/
Clock
Generation
(Alternate)
Digital function
Analog function / Oscillators
Programming, debug, test
External clock / Crystal pins
General Purpose I/O
Ground
LCDPower