Datasheet

368
XMEGA B [DATASHEET]
8291B–AVR–01/2013
Figure 29-3. PDI physical layer enable sequence.
The Reset pin is sampled when the PDI interface is enabled. The reset register is then set according to the state of the
Reset pin, preventing the device from running code after the reset functionality of this pin is disabled.
29.3.2 Disabling
If the clock frequency on PDI_CLK is lower than approximately 10kHz, this is regarded as inactivity on the clock line. This
will automatically disable the PDI. If not disabled by a fuse, the reset function of the Reset (PDI_CLK) pin is enabled
again. This also means that the minimum programming frequency is approximately 10kHz.
29.3.3 Frame Format and Characters
The PDI physical layer uses a frame format defined as one character of eight data bits, with a start bit, a parity bit, and
two stop bits.
Figure 29-4. PDI serial frame format.
Three different characters are used, DATA, BREAK, and IDLE. The BREAK character is equal to a 12-bit length of low
level. The IDLE character is equal to a 12- bit length of high level. The BREAK and IDLE characters can be extended
beyond the 12-bit length.
Figure 29-5. Characters and timing for the PDI physical layer.
Disable RESET function on Reset (PDI_CLK) pin
Activate PDI
PDI_DATA
PDI_CLK
St Start bit, always low
(0-7) Data bits (0 to 7)
P Parity bit, even parity used
Sp1 Stop bit 1, always high
Sp2 Stop bit 2, always high
St
012
3
4567P
Sp1
FRAME
Sp2(IDLE) (St/IDLE)
START
012
3
4567P
STOP
1 IDLE character
BREAK
IDLE
1 DATA character
1 BREAK character