Datasheet

317
XMEGA B [DATASHEET]
8291B–AVR–01/2013
25.5.7 CTRLE – Control register E
 Bits 7:4 – BPS1[3:0]: Blink Segment Selection 1
This bit-field defines the segment which is connected on SEG1 for blinking. Each bit of BPS1[3:0] corresponds to one of
the common terminals.
 Bits 3:0 – BPS0[3:0]: Blink Segment Selection 0
This bit-field defines the segment which is connected on SEG0 for blinking. Each bit of BPS0[3:0] corresponds to one of
the common terminals.
Note: If no segment to blink is selected (BPS1[3:0] = BPS1[3:0] = 0) and if the BLINKEN bit is set, then the full display is
blinking.
25.5.8 CTRLF – Control register F
 Bits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bits 5:0 – FCONT[5:0]: Fine Contrast
FCONT bit-field defines the maximum voltage clk
LCD
on segment and common pins. FCONT is a signed number (two's
complement). New values take effect at the beginning of each frame.
V
LCD
= 3.0 V + ( FCONT[5:0] x 0.016 V )
25.5.9 CTRLG – Control register G
 Bits 7:6 – TDG[1:0]: Type of Digit
(1)
This bit-field specifies the number of segments and segment/common connections used to display a digit. See Table 25-
11 and Figure 25-11 on page 318.
Bit 76543210
+0x06 BPS1[3:0] BPS0[3:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
+0x07
– – FCONT[5:0]
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
+0x08 TDG[1:0] STSEG[5:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 00000000