Datasheet

242
XMEGA B [DATASHEET]
8291B–AVR–01/2013
Figure 19-11.Bus state, state diagram.
After a system reset and/or TWI master enable, the bus state is unknown. The bus state machine can be forced to enter
idle by writing to the bus state bits accordingly. If no state is set by application software, the bus state will become idle
when the first STOP condition is detected. If the master inactive bus timeout is enabled, the bus state will change to idle
on the occurrence of a timeout. After a known bus state is established, only a system reset or disabling of the TWI master
will set the state to unknown.
When the bus is idle, it is ready for a new transaction. If a START condition generated externally is detected, the bus
becomes busy until a STOP condition is detected. The STOP condition will change the bus state to idle. If the master
inactive bus timeout is enabled, the bus state will change from busy to idle on the occurrence of a timeout.
If a START condition is generated internally while in idle state, the owner state is entered. If the complete transaction was
performed without interference, i.e., no collisions are detected, the master will issue a STOP condition and the bus state
will change back to idle. If a collision is detected, the arbitration is assumed lost and the bus state becomes busy until a
STOP condition is detected. A repeated START condition will only change the bus state if arbitration is lost during the
issuing of the repeated START. Arbitration during repeated START can be lost only if the arbitration has been ongoing
since the first START condition. This happens if two masters send the exact same ADDRESS+DATA before one of the
masters issues a repeated START (Sr).
19.5 TWI Master Operation
The TWI master is byte-oriented, with an optional interrupt after each byte. There are separate interrupts for master write
and master read. Interrupt flags can also be used for polled operation. There are dedicated status flags for indicating
ACK/NACK received, bus error, arbitration lost, clock hold, and bus state.
When an interrupt flag is set, the SCL line is forced low. This will give the master time to respond or handle any data, and
will in most cases require software interaction. Figure 19-12 shows the TWI master operation. The diamond shaped
symbols (SW) indicate where software interaction is required. Clearing the interrupt flags releases the SCL line.
P + Timeout
Write ADDRESS
IDLE
(0b01)
S
BUSY
(0b11)
UNKNOWN
(0b00)
OWNER
(0b10)
Arbitration
Lost
Command P
Write
ADDRESS(Sr)
Sr
(S)
RESET
P + Timeout