Datasheet

239
XMEGA B [DATASHEET]
8291B–AVR–01/2013
transferred. If the slave signals a NACK to the data, the master must assume that the slave cannot receive any more
data and terminate the transaction.
Figure 19-6 on page 239 illustrates the master read transaction. The master initiates the transaction by issuing a START
condition followed by an address packet with the direction bit set to one (ADDRESS+R). The addressed slave must
acknowledge the address for the master to be allowed to continue the transaction.
Figure 19-6. Master read transaction.
Assuming the slave acknowledges the address, the master can start receiving data from the slave. There are no
limitations to the number of data packets that can be transferred. The slave transmits the data while the master signals
ACK or NACK after each data byte. The master terminates the transfer with a NACK before issuing a STOP condition.
Figure 19-7 illustrates a combined transaction. A combined transaction consists of several read and write transactions
separated by repeated START conditions (Sr).
Figure 19-7. Combined Transaction.
19.3.7 Clock and Clock Stretching
All devices connected to the bus are allowed to stretch the low period of the clock to slow down the overall clock
frequency or to insert wait states while processing data. A device that needs to stretch the clock can do this by
holding/forcing the SCL line low after it detects a low level on the line.
Three types of clock stretching can be defined, as shown in Figure 19-8.
Figure 19-8. Clock stretching
(1)
.
Note: 1. Clock stretching is not supported by all I
2
C slaves and masters.
If a slave device is in sleep mode and a START condition is detected, the clock stretching normally works during the
wake-up period. For AVR XMEGA devices, the clock stretching will be either directly before or after the ACK/NACK bit,
as AVR XMEGA devices do not need to wake up for transactions that are not addressed to it.
A slave device can slow down the bus frequency by stretching the clock periodically on a bit level. This allows the slave
to run at a lower system clock frequency. However, the overall performance of the bus will be reduced accordingly. Both
S
R
A A AADDRESS DATA DATA P
Transaction
Address Packet Data Packet
N data packets
S A SrA/AR/W DATA A/A
P
ADDRESS DATA R/WADDRESS
Transaction
Address Packet #1 N Data Packets M Data Packets
Address Packet #2
Direction
Direction
A
SDA
SCL
S
ACK/NACKbit 0bit 7 bit 6
Periodic clock
stretching
Random clock
stretching
Wakeup clock
stretching