Datasheet

223
XMEGA B [DATASHEET]
8291B–AVR–01/2013
18.13.5 FIFOWP – FIFO Write Pointer register
 Bit 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 4:0 – FIFOWP[4:0]: FIFO Write Pointer
These bits contain the transaction complete FIFO write pointer. This register must be read only by the CPU or DMA
controller. Writing this register will flush the FIFO write and read pointers.
18.13.6 FIFORP – FIFO Read Pointer register
 Bit 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 4:0 – FIFORP[4:0]: FIFO Read Pointer
These bits contain the transaction complete FIFO read pointer. This register must only be read by the CPU or DMA
controller. Writing this register will flush the FIFO write and read pointer.
18.13.7 EPPTRL – Endpoint Configuration Table Pointer Low
The EPPTRL and EPPTRH registers represent the 16-bit value, EPPTR, that contains the address to the endpoint
configuration table. The pointer to the endpoint configuration table must be aligned to a 16-bit word; i.e., EPPTR[0] must
be zero. Only the number of bits required to address the available internal SRAM memory is implemented for each
device. Unused bits will always be read as zero.
 Bit 7:0 – EPPTR[7:0]: Endpoint Configuration Table Pointer low byte
This register contains the eight lsbs of the endpoint configuration table pointer (EPPTR).
Bit 76543210
+0x04
– – – FIFOWP[4:0]
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value 00000000
Bit 76543210
+0x05
– – – FIFORP[4:0]
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value 00000000
Bit 76543210
+0x06 EPPTR[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R
Initial Value 0 0 0 0 0 0 0 0