Datasheet

222
XMEGA B [DATASHEET]
8291B–AVR–01/2013
 Bit 2 – RWAKEUP: Remote Wake-up
Setting this bit sends an upstream resume on the USB lines if the bus is in the suspend state for at least 5 ms.
 Bit 1 – GNACK: Global NACK
When this bit is set, the USB module will NACK all incoming transactions. Expect for a SETUP packet, this prevents the
USB module from performing any on-chip SRAM access, giving all SRAM bandwidth to the CPU and/or DMA controller.
 Bit 0 – ATTACH: Attach
Setting this bit enables the internal D+ or D- pull-up (depending on the USB speed selection), and attaches the device to
the USB lines. Clearing this bit disconnects the device from the USB lines.
18.13.3 STATUS – Status register
 Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
 Bit 3 – URESUME: Upstream Resume
This flag is set when an upstream resume is sent.
 Bit 2 – RESUME: Resume
This flag is set when a downstream resume is received.
 Bit 1 – SUSPEND: Bus Suspended
This flag is set when the USB lines are in the suspended state (the bus has been idle for at least 3ms).
 Bit 0 – BUSRST: Bus Reset
This flag is set when a reset condition has been detected (the bus has been driven to SE0 for at least 2.5μs).
18.13.4 ADDR – Address register
 Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this
register is written.
 Bit 6:0 – ADDR[6:0]: Device Address
These bits contain the USB address the device will respond to.
Bit 76543210
+0x02
– – – – URESUME RESUME SUSPEND BUSRST
Read/Write RRRRRRRR
Initial Value 00000000
Bit 76543210
+0x03
– ADDR[6:0]
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial Value 00000000