Datasheet

106
XMEGA B [DATASHEET]
8291B–AVR–01/2013
Figure 9-1. Reset system overview.
9.3 Reset Sequence
A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is
active. When all reset requests are released, the device will go through three stages before the device starts running
again:
 Reset counter delay
 Oscillator startup
 Oscillator calibration
If another reset requests occurs during this process, the reset sequence will start over again.
9.3.1 Reset Counter
The reset counter can delay reset release with a programmable period from when all reset requests are released. The
reset delay is timed from the 1kHz output of the ultra low power (ULP) internal oscillator, and in addition 24 System clock
(clk
SYS
) cycles are counted before reset is released. The reset delay is set by the STARTUPTIME fuse bits. The
selectable delays are shown in Table 9-1.
Table 9-1. Reset delay
MCU Status
Register (MCUSR)
Brown-out
Reset
BODLEVEL [2:0]
Delay Counters
TIMEOUT
WDRF
BORF
EXTRF
PORF
ULP
Oscillator
SPIKE
FILTER
Pull-up Resistor
JTRF
Watchdog
Reset
SUT[1:0]
Power-on Reset
Software
Reset
External
Reset
PDI
Reset
SUT[1:0] Number of 1kHz ULP Oscillator Clock Cycles Recommended Usage
00 64K Clk
ULP
+ 24 Clk
SYS
Stable frequency at startup
01 4K Clk
ULP
+ 24 Clk
SYS
Slowly rising power
10 Reserved -
11 24 Clk
SYS
Fast rising power or BOD enabled