8-bit Atmel XMEGA B Microcontroller XMEGA B MANUAL This document contains complete and detailed description of all modules included in the Atmel®AVR®XMEGA® B microcontroller family. The Atmel AVR XMEGA B is a family of lowpower, high-performance, and peripheral-rich CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture with integrated LCD controller.
1. About the Manual This document contains in-depth documentation of all peripherals and modules available for the Atmel AVR XMEGA B microcontroller family. All features are documented on a functional level and described in a general sense. All peripherals and modules described in this manual may not be present in all Atmel AVR XMEGA B devices.
2. Overview The AVR XMEGA B microcontrollers is a family of low-power, high-performance, and peripheral-rich CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the Atmel AVR XMEGA B devices achieve throughputs approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed.
Figure 2-1. Atmel AVR XMEGA B block diagram. PR[0..1] XTAL1 / TOSC1 Power LCD Ground Programming, debug, test Digital function External clock / Crystal pins Analog function / Oscillators General Purpose I/O XTAL2 / TOSC2 Oscillator Circuits/ Clock Generation PORT R (2) Real Time Counter Watchdog Oscillator EVENT ROUTING NETWORK DATA BUS PA[0..
Table 2-1. XMEGA B feature summary overview. Feature Details / sub-family B1 B3 Total 100 64 Programmable I/O pins 53 36 Program memory (KB) 64 - 128 64 - 128 Boot memory (KB) 4-8 4-8 SRAM (KB) 4-8 4-8 EEPROM 2 2-4 General purpose registers 16 16 100A 64A – 64M2 100C1/100C2 – Pins, I/O Memory TQFP Package QFN /VQFN BGA QTouch Sense channels 56 56 DMA Controller Channels 2 2 Channels 4 4 QDEC 1 1 0.4 - 16MHz XOSC Yes Yes 32.
Feature Details / sub-family B1 B3 AES-128 Yes Yes DES Yes Yes CRC-16 Yes Yes CRC-32 Yes Yes Segments 40 25 Common terminals 4 4 2 1 Resolution (bits) 12 12 Sampling speed (kbps) 300 300 Input channels per ADC 16 8 Conversion channels 1 1 4 2 PDI Yes Yes JTAG Yes Yes Boundary scan Yes Yes Crypto /CRC Liquid Crystal Display Controller (LCD) Analog to Digital Converter (ADC) Analog Comparator (AC) Program and Debug Interface XMEGA B [DATASHEET] 8291B–AVR–01/
3. 3.1 Atmel AVR CPU Features 8/16-bit, high-performance Atmel AVR RISC CPU 142 instructions Hardware multiplier 32x8-bit registers directly connected to the ALU Stack in RAM Stack pointer accessible in I/O memory space Direct addressing of up to 16MB of program memory and 16MB of data memory True 16/24-bit access to 16/24-bit I/O registers Efficient support for 8-, 16-, and 32-bit arithmetic Configuration change protection of system-critical features 3.
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation. The ALU is directly connected to the fast-access register file.
3.5 Program Flow After reset, the CPU starts to execute instructions from the lowest address in the flash program memory ‘0.’ The program counter (PC) addresses the next instruction to be fetched. Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
3.7 Status Register The status register (SREG) contains information about the result of the most recently executed arithmetic or logic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
Figure 3-4. AVR CPU general purpose working registers. 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 … R13 0x0D General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11 … R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte The register file is located in a separate address space, and so the registers are not accessible as data memory. 3.9.
The lowest register address holds the least-significant byte (LSB), and the highest register address holds the mostsignificant byte (MSB). In the different addressing modes, these address registers function as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 3.10 RAMP and Extended Indirect Registers In order to access program memory or data memory above 64KB, the address pointer must be larger than 16 bits.
3.10.3 EIND - Extended Indirect Register EIND is concatenated with the Z-register to enable indirect jump and call to locations above the first 128KB (64K words) of the program memory. Figure 3-8. The combined EIND + Z register. Bit (Individually) 7 0 Bit (D-pointer) 3.11 23 0 7 EIND 7 ZH 16 15 0 ZL 8 7 0 Accessing 16-bit Registers The AVR data bus is 8 bits wide, and so accessing 16-bit registers requires atomic operations.
3.12.2 Sequence for execution of protected SPM/LPM 1. The application code writes the signature for the execution of protected SPM/LPM to the CCP register. 2. Within four instruction cycles, the application code must execute the appropriate instruction. The protected change is immediately disabled if the CPU performs write operations to the data memory or if the SLEEP instruction is executed.
3.14 Register Descriptions 3.14.1 CCP – Configuration Change Protection register Bit 7 6 5 4 3 2 1 0 Read/Write W W W W W W R/W R/W Initial Value 0 0 0 0 0 0 0 0 +0x04 CCP[7:0] Bit 7:0 – CCP[7:0]: Configuration Change Protection The CCP register must be written with the correct signature to enable change of the protected I/O register or execution of the protected instruction for a maximum period of four CPU instruction cycles.
3.14.3 RAMPX – Extended X-Pointer register This register is concatenated with the X-register for indirect addressing (LD/LDD/ST/STD) of the whole data memory space on devices with more than 64KB of data memory. This register is not available if the data memory, including external memory, is less than 64KB.
3.14.6 EIND – Extended Indirect register This register is concatenated with the Z-register for enabling extended indirect jump (EIJMP) and call (EICALL) to the whole program memory space on devices with more than 128KB of program memory. The register should be used for jumps to addresses below 128KB if ECALL/EIJMP are used, and it will not be used if CALL and IJMP commands are used. For jump or call to addresses below 128KB, this register is not used.
3.14.9 SREG – Status Register The status register (SREG) contains information about the result of the most recently executed arithmetic or logic instruction. Bit 7 6 5 4 3 2 1 0 +0x0F I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 – I: Global Interrupt Enable The global interrupt enable bit must be set for interrupts to be enabled.
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4. Memories 4.
All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized in two main sections, the application section and the boot loader section, as shown in Figure 4-1 on page 21. The sizes of the different sections are fixed, but device-dependent. These two sections have separate lock bits, and can have different levels of protection.
4.3.4 Production Signature Row The production signature row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to the corresponding peripheral registers from software.
Figure 4-2. Data memory map. Start/End Address Data Memory 0x0000 I/O Memory (Up to 4 KB) 0x1000 EEPROM (Up to 4 KB) 0x2000 Internal SRAM (Up to 8 KB) I/O memory, EEPROM, and SRAM will always have the same start addresses for all XMEGA devices. 4.6 Internal SRAM The internal SRAM always starts at hexadecimal address 0x2000. SRAM is accessed by the CPU using the load (LD/LDS/LDD) and store (ST/STS/STD) instructions. 4.7 EEPROM XMEGA devices have EEPROM for nonvolatile data storage.
the CPU can access the EEPROM memory while the DMA controller is transferring data from internal SRAM to I/O memory. The USB module acts as a bus master, and is connected directly to internal SRAM through a pseudo-dual-port (PDP) interface. Figure 4-3. Bus access.
4.12 JTAG Disable It is possible to disable the JTAG interface from the application software. This will prevent all external JTAG access to the device until the next device reset or until JTAG is enabled again from the application software. As long as JTAG is disabled, the I/O pins required for JTAG can be used as normal I/O pins. 4.13 I/O Memory Protection Some features in the device are regarded as critical for safety in some applications.
4.14 Register Description – NVM Controller 4.14.1 ADDR0 – Address register 0 The ADDR0, ADDR1, and ADDR2 registers represent the 24-bit value, ADDR. This is used for addressing all NVM sections for read, write, and CRC operations. Bit 7 6 5 4 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 3 2 1 0 +0x00 ADDR[7:0] Bit 7:0 – ADDR[7:0]: Register Byte 0 This register gives the address low byte when accessing NVM locations. 4.14.
4.14.5 DATA1 – Data register 1 Bit 7 6 5 4 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 3 2 1 0 +0x05 DATA[15:8] Bit 7:0 – DATA[15:8]: Data Register Byte 1 This register gives the data value byte 1 when accessing NVM locations. 4.14.
4.14.9 CTRLB – Control register B Bit 7 6 5 4 3 2 1 0 +0x0C – – – – EEMAPEN FPRM EPRM SPMLOCK Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. Bit 3 – EEMAPEN: EEPROM Data Memory Mapping Enable Setting this bit enables data memory mapping of the EEPROM section.
4.14.11 STATUS – Status register Bit +0x04 7 6 5 4 3 2 1 0 NVMBUSY FBUSY – – – – EELOAD FLOAD Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 Bit 7 – NVMBUSY: Nonvolatile Memory Busy The NVMBUSY flag indicates if the NVM (Flash, EEPROM, lock bit) is being programmed. Once an operation is started, this flag is set and remains set until the operation is completed. The NVMBUSY flag is automatically cleared when the operation is finished.
4.14.12 LOCKBITS – Lock Bits register Bit 7 +0x07 6 5 BLBB[1:0] 4 3 BLBA[1:0] 2 1 BLBAT[1:0] 0 LB[1:0] Read/Write R R R R R R R R Initial Value 1 1 1 1 1 1 1 1 This register is a mapping of the NVM lock bits into the I/O memory space, which enables direct read access from the application software. Refer to “LOCKBITS – Lock Bits register” on page 34 for a description. 4.15 Register Descriptions – Fuses and Lock Bits 4.15.
4.15.3 FUSEBYTE2 – Fuse Byte 2 Bit +0x02 7 6 5 4 3 2 1 0 – BOOTRST TOSCSEL – – – Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 1 1 1 1 BODPD[1:0] Bit 7 – Reserved This fuse bit is reserved. For compatibility with future devices, always write this bit to one when this register is written.
4.15.4 FUSEBYTE4 – Fuse Byte 4 Bit 7 +0x04 6 5 4 3 2 0 – – – RSTDISBL WDLOCK JTAGEN Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 1 1 1 0 STARTUPTIME[1:0] 1 Bit 7:5 – Reserved These fuse bits are reserved. For compatibility with future devices, always write these bits to one when this register is written. Bit: 4 – RSTDISBL: External Reset Disable This fuse can be programmed to disable the external reset pin functionality.
Table 4-6. JTAG Enabled JTAGEN Description 0 JTAG enabled 1 JTAG disabled 4.15.5 FUSEBYTE5 – Fuse Byte 5 Bit 7 6 5 +0x05 – – BODACT[1:0] Read/Write R/W R/W R R R/W R/W R/W R/W Initial Value 1 1 – – – – – – 4 3 2 EESAVE 1 0 BODLEVEL[2:0] Bit 7:6 – Reserved These bits are reserved. For compatibility with future devices, always write these bits to one when this register is written.
4.15.6 LOCKBITS – Lock Bits register Bit 7 +0x07 6 5 BLBB[1:0] 4 3 BLBA[1:0] 2 1 BLBAT[1:0] 0 LB[1:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 1 1 1 1 Bit 7:6 – BLBB[1:0]: Boot Lock Bit Boot Loader Section These lock bits control the software security level for accessing the boot loader section. The BLBB bits can only be written to a more strict locking. Resetting the BLBB bits is possible only by executing a chip erase command. Table 4-9.
Bit 3:2 – BLBAT[1:0]: Boot Lock Bit Application Table Section These lock bits control the software security level for accessing the application table section for software access. The BLBAT bits can only be written to a more strict locking. Resetting the BLBAT bits is possible only by executing a chip erase command. Table 4-11. Boot lock bit for the application table section. BLBAT[1:0] Group Configuration 11 NOLOCK No lock – no restrictions for SPM and (E)LPM accessing the application table section.
4.16 Register Description – Production Signature Row 4.16.1 RCOSC2M – Internal 2MHz Oscillator Calibration register Bit 7 6 5 4 Read/Write R R R R Initial Value x x x x +0x00 3 2 1 0 R R R R x x x x RCOSC2M[7:0] Bit 7:0 – RCOSC2M[7:0]: Internal 2MHz Oscillator Calibration Value This byte contains the oscillator calibration value for the internal 2MHz oscillator. Calibration of the oscillator is performed during production testing of the device.
4.16.5 RCOSC32MA – Internal 32MHz RC Oscillator Calibration register Bit 7 6 5 4 Read/Write R R R R Initial Value x x x x +0x04 3 2 1 0 R R R R x x x x RCOSC32MA[7:0] Bit 7:0 – RCOSC32MA[7:0]: Internal 32MHz Oscillator Calibration Value This byte contains the oscillator calibration value for the internal 32MHz oscillator. Calibration of the oscillator is performed during production testing of the device.
4.16.9 LOTNUM3- Lot Number register 3 Bit 7 6 5 4 Read/Write R R R R Initial Value x x x x +0x0B 3 2 1 0 R R R R x x x x 3 2 1 0 LOTNUM3[7:0] Bit 7:0 – LOTNUM3[7:0]: Lot Number Byte 3 This byte contains byte 3 of the lot number for the device. 4.16.
4.16.13 COORDX0 – Wafer Coordinate X register 0 COORDX0, COORDX1, COORDY0, and COORDY1 contain the wafer X and Y coordinates for each device. Together with the lot number and wafer number, this gives a serial number for each device. Bit 7 6 5 4 +0x12 3 2 1 0 COORDX0[7:0] Read/Write R R R R R R R R Initial Value x x x x x x x x 3 2 1 0 Bit 7:0 – COORDX0[7:0]: Wafer Coordinate X Byte 0 This byte contains byte 0 of wafer coordinate X for the device. 4.16.
4.16.17 USBCAL0 – USB Calibration register 0 USBCAL0 and USBCAL1 contain the calibration value for the USB pins. Calibration is done during production to enable operation without requiring external components on the USB lines for the device. The calibration bytes are not loaded automatically into the USB calibration registers, and so this must be done from software.
4.16.21 ADCACAL1 – ADCA Calibration register 1 Bit 7 6 5 4 Read/Write R R R R Initial Value x x x x +0x21 3 2 1 0 R R R R x x x x ADCACAL1[7:0] Bit 7:0 – ADCACAL1[7:0]: ADCA Calibration Byte 1 This byte contains byte 1 of the ADCA calibration data, and must be loaded into the ADCA CALH register. 4.16.22 ADCBCAL0 – ADCB Calibration register 0 ADCBCAL0 and ADCBCAL1 contains the calibration value for the analog-to-digital converter B (ADCB).
4.16.25 TEMPSENSE1 – Temperature Sensor Calibration Register 1 Bit 7 6 5 4 Read/Write R R R R Initial Value 0 0 0 0 +0x2F 3 2 1 0 R R R R x x x x TEMPSENSE1[7:0] Bit 7:0 – TEMPSENSE1[7:0]: Temperature Sensor Calibration Byte 1 This byte contains byte 1 of the temperature measurement. 4.17 Register Description – General Purpose I/O Memory 4.17.
4.18.3 DEVID2 – Device ID register 2 Bit 7 6 5 4 3 2 1 0 Read/Write R R R R R R R R Initial Value 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 3 2 1 0 +0x02 DEVID2[7:0] Bit 7:0 – DEVID2[7:0]: Device ID Byte 2 Byte 2 of the device ID indicates the device number. 4.18.
4.18.7 ANAINIT – Analog Initialization register Bit 7 6 5 4 3 2 1 0 +0x07 – – – – STARTUPDLYB[1:0] STARTUPDLYA[1:0] Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
4.18.9 AWEXLOCK – Advanced Waveform Extension Lock register Bit 7 6 5 4 3 2 1 0 +0x09 – – – – – – – AWEXCLOCK Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
4.19 Register Summary - NVM Controller Address Name +0x00 +0x01 +0x02 +0x03 +0x04 +0x05 +0x06 +0x07 +0x08 +0x09 +0x0A +0x0B +0x0C +0x0D +0x0E +0x0F +0x10 ADDR0 ADDR1 ADDR2 Reserved DATA0 DATA1 DATA2 Reserved Reserved Reserved CMD CTRLA CTRLB INTCTRL Reserved STATUS LOCKBITS 4.
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5. DMAC - Direct Memory Access Controller 5.
Figure 5-1. DMA Overview. DMA Channel 0 DMA trigger / Event CTRLA CTRLB TRIGSRC Enable Burst Control Logic TRFCNT REPCNT Arbitration R/W Master port Arbiter DESTADDR SRCADDR Read BUF Write DMA Channel 1 Bus matrix CTRL Slave port Read / Write 5.3 DMA Transaction A complete DMA read and write operation between memories and/or peripherals is called a DMA transaction.
5.4 Transfer Triggers DMA transfers can be started only when a DMA transfer request is detected. A transfer request can be triggered from software, from an external trigger source (peripheral), or from an event. There are dedicated source trigger selections for each DMA channel. The available trigger sources may vary from device to device, depending on the modules or peripherals that exist in the device. Using a transfer trigger for a module or peripherals that does not exist will have no effect.
5.9 Error detection The DMA controller can detect erroneous operation. Error conditions are detected individually for each DMA channel, and the error conditions are: Write to memory mapped EEPROM locations Reading EEPROM when the EEPROM is off (sleep entered) DMA controller or a busy channel is disabled in software during a transfer 5.10 Software Reset Both the DMA controller and a DMA channel can be reset from the user software.
5.13 Register Description – DMA Controller 5.13.1 CTRL – Control register Bit +0x00 7 6 5 4 3 2 1 0 ENABLE RESET – – – DBUFMODE – PRIMODE Read/Write R/W R/W R R R R/W R R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 – ENABLE: Enable Setting this bit enables the DMA controller. If the DMA controller is enabled and this bit is written to zero, the ENABLE bit is not cleared before the internal transfer buffer is empty, and the DMA data transfer is aborted.
Bit 5:4 – CHnERRIF[1:0]: Channel n Error Interrupt Flag If an error condition is detected on DMA channel n, the CHnERRIF flag will be set. Writing a one to this bit location will clear the flag. Bit 3:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
5.13.5 TEMPH – Temporary Register High Bit 7 6 5 4 +0x07 3 2 1 0 TEMP[15:8] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:0 – TEMP[15:8]: Temporary Register This register is used when reading and writing 24-bit registers in the DMA controller. Byte 2 of the 24-bit register is stored when it is written by the CPU. Byte 2 of the 24-bit register is stored here when byte 1 is read by the CPU.
Bit 1:0 – BURSTLEN[1:0]: Burst Mode These bits decide the DMA channel burst mode according to Table 5-2 on page 56. These bits cannot be changed if the channel is busy. Table 5-2. DMA channel burst mode BURSTLEN[1:0] Group Configuration 00 1BYTE 1 byte burst mode 01 2BYTE 2 bytes burst mode 10 4BYTE 4 bytes burst mode 11 8BYTE 8 bytes burst mode Table 5-3. Description Summary of triggers, transaction complete flag and channel disable according to DMA channel configuration.
Bit 6 – CHPEND: Channel Pending If a block transfer is pending on the DMA channel, the CHPEND flag will be read as one. This flag is automatically cleared when the transfer starts or if the transfer is aborted. Bit 5 – ERRIF: Error Interrupt Flag If an error condition is detected on the DMA channel, the ERRIF flag will be set and the optional interrupt is generated.
Bit 5:4 – SRCDIR[1:0]: Channel Source Address Mode These bits decide the DMA channel source address mode according to Table 5-5. These bits cannot be changed if the channel is busy. Table 5-5. DMA channel source address mode settings.
5.14.4 TRIGSRC – Trigger Source Bit 7 6 5 4 Read/Write R/W R/W R/W R/W Initial Value 0 0 0 0 +0x03 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 TRIGSRC[7:0] Bit 7:0 – TRIGSRC[7:0]: Channel Trigger Source Select These bits select which trigger source is used for triggering a transfer on the DMA channel. A zero value means that the trigger source is disabled.
Table 5-9. DMA trigger source offset values for event system triggers. TRGSRC Offset Value Group Configuration Description +0x00 CH0 Event channel 0 +0x01 CH1 Event channel 1 +0x02 CH2 Event channel 2 Table 5-10. DMA trigger source offset values for timer/ counter triggers.
5.14.6 TRFCNTH – Channel Block Transfer Count register High Reading and writing 16-bit values requires special attention. For details, refer to “Accessing 16-bit Registers” on page 13. Bit 7 6 5 +0x05 4 3 2 1 0 TRFCNT[15:8] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:0 – TRFCNT[15:8]: Channel n Block Transfer Count high byte These bits hold the MSB of the 16-bit block transfer count. The default value of this register is 0x1.
5.14.9 SRCADDR1 – Channel Source Address 1 Bit 7 6 5 4 Read/Write R/W R/W R/W R/W Initial Value 0 0 0 0 +0x09 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 SRCADDR[15:8] Bit 7:0 – SRCADDR[15:8]: Channel Source Address byte 1 These bits hold byte 1 of the 24-bit source address. 5.14.10 SRCADDR2 – Channel Source Address 2 Reading and writing 24-bit values require special attention. For details, refer to “Accessing 24- and 32-bit Registers” on page 13.
5.14.12 DESTADDR1 – Channel Destination Address 1 Bit 7 6 5 +0x0D 4 3 2 1 0 DESTADDR[15:8] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:0 – DESTADDR[15:8]: Channel Destination Address byte 1 These bits hold byte 1 of the 24-bit source address. 5.14.13 DESTADDR2 – Channel Destination Address 2 Reading and writing 24-bit values require special attention. For details, refer to “Accessing 24- and 32-bit Registers” on page 13.
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6. Event System 6.
Figure 6-1. Event system overview and connected peripherals. CPU / Software DMA Controller Event Routing Network clkPER Prescaler Real Time Counter ADC Event System Controller Timer / Counters AC USB Port pins IRCOM The event routing network consists of four software-configurable multiplexers that control how events are routed and used. These are called event channels, and allow for up to four parallel event configurations and routings. The maximum routing latency is two peripheral clock cycles.
Figure 6-2. Example of event source, generator, user, and action. Event Generator Event User Timer/Counter ADC Compare Match Over-/Underflow | Event Routing Network Syncsweep Single Conversion Error Event Action Selection Event Source Event Action Events can also be generated manually in software. 6.3.1 Signaling Events Signaling events are the most basic type of event. A signaling event does not contain any information apart from the indication of a change in a peripheral.
Table 6-1. 6.4 Manually generated events and decoding of events. STROBE DATA Data Event User Signaling Event User 0 0 No event No event 0 1 Data event 01 No event 1 0 Data event 02 Signaling event 1 1 Data event 03 Signaling event Event Routing Network The event routing network routes the events between peripherals. It consists of eight multiplexers (CHnMUX), which can each be configured to route any event source to any event users.
Figure 6-3. Event routing network.
It takes a maximum of two peripheral clock cycles from when an event is generated until the event actions in other peripherals are triggered. This ensures short and 100% predictable response times, independent of CPU or DMA controller load or software revisions. 6.6 Filtering Each event channel includes a digital filter. When this is enabled, an event must be sampled with the same value for a configurable number of system clock cycles before it is accepted.
In order to know the absolute rotary displacement, a third index signal (QINDX) can be used. This gives an indication once per revolution. 6.7.2 QDEC Setup For a full QDEC setup, the following is required: Tho or three I/O port pins for quadrature signal input Two event system channels for quadrature decoding One timer/counter for up, down, and optional index count The following procedure should be used for QDEC setup: 1. Choose two successive pins on a port as QDEC phase inputs. 2.
6.8 Register Description 6.8.1 CHnMUX – Event Channel n Multiplexer register Bit 7 6 5 4 Read/Write R/W R/W R/W R/W Initial Value 0 0 0 0 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 CHnMUX[7:0] Bit 7:0 – CHnMUX[7:0]: Channel Multiplexer These bits select the event source according to Table 6-3. This table is valid for all XMEGA devices regardless of whether the peripheral is present or not.
CHnMUX[7:4] CHnMUX[3:0] Event Source 0010 1 X X X (Reserved) 0011 X X X X (Reserved) 0100 X X X X (Reserved) 0101 0 n PORTA_PINn(1) PORTA pin n (n= 0, 1, 2 ... or 7) (1) 0101 1 n PORTB_PINn PORTB pin n (n= 0, 1, 2 ... or 7) 0110 0 n PORTC_PINn(1) PORTC pin n (n= 0, 1, 2 ... or 7) 0110 1 n PORTD_PINn(1) PORTD pin n (n= 0, 1, 2 ... or 7) 0111 0 n PORTE_PINn(1) PORTE pin n (n= 0, 1, 2 ... or 7) n (1) PORTF pin n (n= 0, 1, 2 ...
6.8.2 CHnCTRL – Event Channel n Control register Bit 7 6 – 5 QDIRM[1:0] (1) 4 3 QDIEN (1) 2 (1) QDEN 1 0 DIGFILT[2:0] – – – – – Read/Write R R/W R/W R/W R/W R/W R/W R Initial Value 0 0 0 0 0 0 0 0 Note: 1. DIGFILT[2:0] Only available for CH0CTRL and CH2CTRL. These bits are reserved in CH1CTRL and CH3CTRL. Bit 7 – Reserved This bit is reserved and will always be read as zero.
Table 6-6. 6.8.3 Digital filter coefficient values (Continued). DIGFILT[2:0] Group Configuration Description 011 4SAMPLES Four samples 100 5SAMPLES Five samples 101 6SAMPLES Six samples 110 7SAMPLES Seven samples 111 8SAMPLES Eight samples STROBE – Strobe register If the STROBE register location is written, each event channel will be set according to the STROBE[n] and corresponding DATA[n] bit settings, if any are unequal to zero.
6.
7. System Clock and Clock Options 7.1 Features Fast start-up time Safe run-time clock switching Internal oscillators: 32MHz run-time calibrated oscillator 2MHz run-time calibrated oscillator 32.768kHz calibrated oscillator 32kHz ultra low power (ULP) oscillator with 1kHz output External clock options 0.4MHz - 16MHz crystal oscillator 32.
Figure 7-1. The clock system, clock sources, and clock distribution. Real Time Counter LCD Peripherals RAM Non-Volatile Memory AVR CPU clkPER clkCPU clkPER2 clkPER4 clkRTC clkLCD USB clkUSB System Clock Prescalers Watchdog Timer Prescaler clkSYS Brown-out Detector System Clock Multiplexer (SCLKSEL) DIV32 DIV32 DIV32 RTCSRC USBSRC PLL DIV4 PLLSRC XTAL2 0.4 – 16 MHz XTAL XTAL1 32.768 kHz TOSC TOSC2 32.768 kHz Int. OSC TOSC1 32 kHz Int. ULP 32 MHz Int. Osc 2 MHz Int.
7.3 Clock Distribution Figure 7-1 on page 78 presents the principal clock distribution system used in XMEGA devices. 7.3.1 System Clock - ClkSYS The system clock is the output from the main system clock selection. This is fed into the prescalers that are used to generate all internal clocks except the asynchronous and USB clocks. 7.3.2 CPU Clock - ClkCPU The CPU clock is routed to the CPU and nonvolatile memory. Halting the CPU clock inhibits the CPU from executing instructions. 7.3.
7.4.1.3 32MHz Run-time Calibrated Oscillator The 32MHz run-time calibrated internal oscillator is a high-requency oscillator. It is calibrated during production to provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy. This oscillator can also be adjusted and calibrated to any frequency between 30MHz and 55MHz.
7.4.2.3 32.768kHz Crystal Oscillator A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low frequency oscillator input circuit. A typical connection is shown in Figure 7-4 on page 81. A low power mode with reduced voltage swing on TOSC2 is available. This oscillator can be used as a clock source for the system clock, RTC and LCD, and as the DFLL reference clock. Figure 7-4. 32.768kHz crystal oscillator connection.
7.6 PLL with 1x-31x Multiplication Factor The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a userselectable multiplication factor of from 1 to 31. The output frequency, fOUT, is given by the input frequency, fIN, multiplied by the multiplication factor, PLL_FAC. f OUT = f IN PLL_FAC Four different clock sources can be chosen as input to the PLL: 2MHz internal oscillator 32MHz internal oscillator divided by 4 0.
Figure 7-6. DFLL reference clock selection. XOSCSEL TOSC1 TOSC2 XTAL1 PC[7:0] 32.768 kHz Crystal Osc External Clock 32.768 kHz Int. Osc DIV32 DIV32 USB Start of Frame clkRC2MCREF clkRC32MCREF DFLL32M 32 MHz Int. RCOSC DFLL2M 2 MHz Int. RCOSC The ideal counter value representing the frequency ratio between the internal oscillator and a 1.024kHz reference clock is loaded into the DFLL oscillator compare register (COMP) during reset.
Figure 7-7. Automatic run-time calibration. clkRCnCREF DFLL CNT tRCnCREF COMP 0 Frequency OK RCOSC fast, CALA decremented RCOSC slow, CALA incremented The DFLL will stop when entering a sleep mode where the oscillators are stopped. After wake up, the DFLL will continue with the calibration value found before entering sleep. The reset value of the DFLL calibration register can be read from the production signature row.
7.9 Register Description – Clock 7.9.1 CTRL – Control register Bit 7 6 5 4 3 2 1 0 +0x00 – – – – – Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SCLKSEL[2:0] Bit 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. Bit 2:0 – SCLKSEL[2:0]: System Clock Selection These bits are used to select the source for the system clock.
Bit 6:2 – PSADIV[4:0]: Prescaler A Division Factor These bits define the division ratio of the clock prescaler A according to Table 7-2. These bits can be written at run-time to change the frequency of the ClkPER4 clock relative to the system clock, ClkSYS. Table 7-2. Prescaler A division factor.
7.9.3 LOCK – Lock register Bit 7 6 5 4 3 2 1 0 +0x02 – – – – – – – LOCK Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Bit 0 – RTCEN: RTC and LCD Clock Source Enable Setting the RTCEN bit enables the selected clock source for the real-time counter (RTC) and LCD. 7.9.5 USBSCTRL – USB Control register Bit 7 6 +0x04 – – Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 5 4 3 2 USBPSDIV[2:0] 1 USBSRC[1:0] 0 USBSEN Bit 7:6 – Reserved These bits are unused and reserved for future use.
7.10 Register Description – Oscillator 7.10.1 CTRL – Control register Bit 7 6 5 4 3 2 1 0 +0x00 – – – PLLEN XOSCEN RC32KEN RC32MEN RC2MEN Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 1 Bit 7:5 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. Bit 4 – PLLEN: PLL Enable Setting this bit enables the PLL.
Bit 0 – RC2MRDY: 2MHz Internal Oscillator Ready This flag is set when the 2MHz internal oscillator is stable and is ready to be used as the system clock source. 7.10.3 XOSCCTRL – XOSC Control register Bit 7 6 5 4 3 2 1 0 XOSCPWR +0x02 FRQRANGE[1:0] X32KLPM XOSCSEL[3:0] XOSCSEL[4] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:6 – FRQRANGE[1:0]: 0.
Table 7-8. External oscillator selection and start-up time. XOSCSEL[4:0] Group configuration (3) 00000 EXTCLK Start-up time External Clock from XTAL1 pin 6 CLK nnn 01 EXTCLK_Cn(3) External Clock from Port C pin n 6 CLK 00010 32KHZ(3) 32.768kHz TOSC 16K CLK x(4)0011 XTAL_256CLK(1) 0.4MHz - 16MHz XTAL 256 CLK x 0111 XTAL_1KCLK (2) 0.4MHz - 16MHz XTAL 1K CLK x(4)1011 XTAL_16KCLK 0.4MHz - 16MHz XTAL 16K CLK (4) Notes: Selected clock source 1. 2. 3. 4.
7.10.5 RC32KCAL – 32kHz Oscillator Calibration register Bit 7 6 5 4 Read/Write R/W R/W R/W R/W Initial Value x x x x +0x04 3 2 1 0 R/W R/W R/W R/W x x x x RC32KCAL[7:0] Bit 7:0 – RC32KCAL[7:0]: 32.768kHz Internal Oscillator Calibration byte This register is used to calibrate the 32.768kHz internal oscillator. A factory-calibrated value is loaded from the signature row of the device and written to this register during reset, giving an oscillator frequency close to 32.768kHz.
Bit 2:1 – RC32MCREF[1:0]: 32MHz Oscillator Calibration Reference These bits are used to select the calibration source for the 32MHz DFLL according to the Table 7-10. These bits will select only which calibration source to use for the DFLL. In addition, the actual clock source that is selected must enabled and configured for the calibration to function. Table 7-10. 32MHz oscillator reference design. RC32MCREF[1:0] Group Configuration Description 00 RC32K 01 XOSC32 32.
Bit 7 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. Bit 6:0 – CALA[6:0]: DFLL Calibration bits These bits hold the part of the oscillator calibration value that is used for automatic runtime calibration.
7.11.4 COMP1 – Compare register byte 1 The COMP1 and COMP2 register pair represent the frequency ratio between the oscillator and the reference clock. The initial value for these registers is the ratio between the internal oscillator frequency and a 1.024kHz reference.
7.12 Register Summary – Clock Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 +0x00 +0x01 +0x02 +0x03 +0x04 +0x05 +0x06 +0x07 CTRL PSCTRL LOCK RTCCTRL USBSCTRL Reserved Reserved Reserved – – – – – – – – – – – – – – – – – – – – PSADIV[4:0] – – USBPSDIV[2:0] – – – Bit 4 Bit 3 7.
8. Power Management and Sleep Modes 8.1 Features Power management for adjusting power consumption and functions Five sleep modes Idle Power down Power save Standby Extended standby Power reduction register to disable clock and turn off unused peripherals in active and idle modes 8.2 Overview Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements. This enables the XMEGA microcontroller to stop unused modules to save power.
Active clock domains and wake-up sources in the different sleep modes. Idle X X X X Standby Extended standby X X X X X X X X X X X X X X X X X X X X X All Interrupts RTC and LCD Clock Interrupts TWI Address Match Interrupts USB Resume RTC Clock Source X Power down Power save Wake-up Sources Asynchronous Port Interrupts Oscillators RTC and LCD Clock CPU Clock Sleep Modes Peripheral and USB Clock Active Clock Domain System Clock Source Table 8-1.
8.3.5 Extended Standby Mode Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time. 8.4 Power Reduction Registers The power reduction (PR) registers provide a method to stop the clock to individual peripherals. When this is done, the current state of the peripheral is frozen and the associated I/O registers cannot be read or written.
8.5.6 On-chip Debug Systems If the On-chip debug system is enabled and the chip enters sleep mode, the main clock source is enabled and hence always consumes power. In the deeper sleep modes, this will contribute significantly to the total current consumption.
8.6 Register Description – Sleep 8.6.1 CTRL – Control Register Bit 7 6 5 4 3 2 1 0 +0x00 – – – – Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SMODE[2:0] SEN Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. Bit 3:1 – SMODE[2:0]: Sleep Mode selection These bits select sleep modes according to Table 8-2. Table 8-2.
Bit 6 – USB: USB Module Setting this bit stops the clock to the USB module. When this bit is cleared, the peripheral should be reinitialized to ensure proper operation. Bit 5 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. Bit 4 – AES: AES Module Setting this bit stops the clock to the AES module.
Bit 6 – TWI: Two-Wire Interface Setting this bit stops the clock to the two-wire interface. When this bit is cleared, the peripheral should be reinitialized to ensure proper operation. Bit 5 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. Bit 4 – USART0 Setting this bit stops the clock to USART0.
8.8 Register Summary - Sleep Address Name Bit 7 Bit 6 Bit 5 Bit 4 +0x00 CTRL – – – – 8.
9. Reset System 9.1 Features Reset the microcontroller and set it to initial state when a reset source goes active Multiple reset sources that cover different situations Power-on reset External reset Watchdog reset Brownout reset PDI reset Software reset Asynchronous operation No running system clock in the device is required for reset Reset status register for reading the reset source from the application code 9.
Figure 9-1. Reset system overview. Power-on Reset BODLEVEL [2:0] PORF BORF EXTRF WDRF JTRF MCU Status Register (MCUSR) Brown-out Reset Pull-up Resistor SPIKE FILTER External Reset PDI Reset Software Reset Watchdog Reset ULP Oscillator Delay Counters TIMEOUT SUT[1:0] 9.3 Reset Sequence A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is active.
Whenever a reset occurs, the clock system is reset and the internal 2MHz internal oscillator is chosen as the source for ClkSYS. 9.3.2 Oscillator Startup After the reset delay, the 2MHz internal oscillator clock is started, and its calibration values are automatically loaded from the calibration row to the calibration registers. 9.4 Reset Sources 9.4.1 Power-on Reset A power-on reset (POR) is generated by an on-chip detection circuit.
When VCC increases above the trigger level (VBOT+ in Figure 9-4), the reset counter starts the MCU after the timeout period, tTOUT, has expired. The trigger level has a hysteresis to ensure spike free brownout detection. The hysteresis on the detection level should be interpreted as VBOT+= VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2. The BOD circuit will detect a drop in VCC only if the voltage stays below the trigger level for longer than tBOD. Figure 9-4. Brownout detection reset.
reduce the power consumption compared to the enabled mode, but a fall in the VCC level between two positive edges of the 1kHz ULP oscillator output will not be detected. If a brownout is detected in this mode, the BOD circuit is set in enabled mode to ensure that the device is kept in reset until VCC is above VBOT again The BODACT fuse determines the BOD setting for active mode and idle mode, while the BODPD fuse determines the brownout detection setting for all sleep modes, except idle mode. Table 9-3. 9.
Figure 9-6. Watchdog reset. CC 1-2 2MHz Cycles For information on configuration and use of the WDT, refer to the “WDT – Watchdog Timer” on page 113. 9.4.5 Software Reset The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset control register.The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any instruction from when a software reset is requested until it is issued. Figure 9-7.
9.5 Register Description 9.5.1 STATUS – Status register Bit 7 6 5 4 3 2 1 0 +0x00 – – SRF PDIRF WDRF BORF EXTRF PORF Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value - - - - - - - - Bit 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. Bit 5 – SRF: Software Reset Flag This flag is set if a software reset occurs.
When this bit is set, a software reset will occur. The bit is cleared when a reset is issued. This bit is protected by the configuration change protection mechanism. For details, refer to “Configuration Change Protection” on page 13. 9.
10. WDT – Watchdog Timer 10.1 Features Issues a device reset if the timer is not reset before its timeout period Asynchronous operation from dedicated oscillator 1kHz output of the 32kHz ultra low power oscillator 11 selectable timeout periods, from 8ms to 8s. Two operation modes: Normal mode Window mode Configuration lock to prevent unwanted changes 10.2 Overview The watchdog timer (WDT) is a system function for monitoring correct program operation.
10.4 Window Mode Operation In window mode operation, the WDT uses two different timeout periods, a "closed" window timeout period (TOWDTW) and the normal timeout period (TOWDT). The closed window timeout period defines a duration of from 8ms to 8s where the WDT cannot be reset. If the WDT is reset during this period, the WDT will issue a system reset. The normal WDT timeout period, which is also 8ms to 8s, defines the duration of the "open" period duirng which the WDT can (and should) be reset.
10.7 Registers Description 10.7.1 CTRL – Control register Bit 7 6 5 4 3 2 1 0 +0x00 – – ENABLE CEN Read/Write (unlocked) R R R/W R/W R/W R/W R/W R/W Read/Write (locked) R R R R R R R R Initial Value (x = fuse) 0 0 X X X X X 0 PER[3:0] Bits 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Note: Reserved settings will not give any timeout. Bit 1 – ENABLE: Enable This bit enables the WDT. Clearing this bit disables the watchdog timer. In order to change this bit, the CEN bit in “CTRL – Control register” on page 115 must be written to one at the same time. This bit is protected by the configuration change protection mechanism, For a detailed description, refer to “Configuration Change Protection” on page 13.
WPER[3:0] Group Configuration Typical Closed Window Periods 1010 8KCLK 8.0s 1011 – Reserved 1100 – Reserved 1101 – Reserved 1110 – Reserved 1111 – Reserved Note: Reserved settings will not give any timeout for the window. Bit 1 – WEN: Window Mode Enable This bit enables the window mode. In order to change this bit, the WCEN bit in “WINCTRL – Window Mode Control register” on page 116 must be written to one at the same time.
11. Interrupts and Programmable Multilevel Interrupt Controller 11.
Figure 11-1. Interrupt controller overview. Interrupt Controller Priority decoder INT LEVEL Peripheral 1 INT REQ INT ACK CPU ”RETI” CPU INT ACK INT LEVEL Peripheral n INT REQ INT ACK CPU INT LEVEL CPU INT REQ INT REQ INT ACK LEVEL Enable CTRL 11.4 STATUS INTPRI Global Interrupt Enable CPU.SREG Wake-up Sleep Controller Interrupts All interrupts and the reset vector each have a separate program vector address in the program memory space.
If an interrupt occurs during execution of a multicycle instruction, this instruction is completed before the interrupt is served. See Figure 11-2 on page 120 for more details. Figure 11-2. Interrupt execution of a multicycle instruction. If an interrupt occurs when the device is in sleep mode, the interrupt execution response time is increased by five clock cycles. In addition, the response time is increased by the start-up time from the selected sleep mode.
11.5 Interrupt level The interrupt level is independently selected for each interrupt source. For any interrupt request, the PMIC also receives the interrupt level for the interrupt. The interrupt levels and their corresponding bit values for the interrupt level configuration of all interrupts is shown in Table 11-1. Table 11-1. Interrupt levels Interrupt Level Configuration Group Configuration Description 00 OFF Interrupt disabled.
Figure 11-3. Static priority. 11.6.2 Round-robin Scheduling To avoid the possible starvation problem for low-level interrupts with static priority, where some interrupts might never be served, the PMIC offers round-robin scheduling for low-level interrupts. When round-robin scheduling is enabled, the interrupt vector address for the last acknowledged low-level interrupt will have the lowest priority the next time one or more interrupts from the low level is requested. Figure 11-4. Round-robin scheduling.
11.7 Interrupt vector locations Table 11-2 shows reset and Interrupt vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 11-2.
11.8 Register Description 11.8.1 STATUS – Status register Bit 7 +0x00 6 5 4 3 2 1 0 NMIEX – – – – HILVLEX MEDLVLEX LOLVLEX Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 Bit 7 – NMIEX: Non-Maskable Interrupt Executing This flag is set if a non-maskable interrupt is executing. The flag will be cleared when returning (RETI) from the interrupt handler. Bit 6:3 – Reserved These bits are unused and reserved for future use.
11.8.3 CTRL – Control register Bit 7 6 5 4 3 2 1 0 RREN IVSEL – – – HILVLEN MEDLVLEN LOLVLEN Read/Write R/W R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 +0x02 Bit 7 – RREN: Round-robin Scheduling Enable When the RREN bit is set, the round-robin scheduling scheme is enabled for low-level interrupts. When this bit is cleared, the priority is static according to interrupt vector address, where the lowest address has the highest priority.
12. I/O Ports 12.
Figure 12-1. General I/O pin functionality. Pull Enable C o n t r o l PINnCTRL Q D R L o g i c Pull Keep Pull Direction Input Disable Wired AND/OR Inverted I/O OUTn Pxn Q D R DIRn Q D R Synchronizer INn Q D R Q D R Digital Input Pin Analog Input/Output 12.3 I/O Pin Use and Configuration Each port has one data direction (DIR) register and one data output value (OUT) register that are used for port pin control. The data input value (IN) register is used for reading the port pins.
configurations with pull-up and pull-down have active resistors only when the pin is set as input. This feature eliminates unnecessary power consumption. For wired-AND and wired-OR configuration, the optional pull-up and pull-down resistors are active in both input and output directions. Since pull configuration is configured through the pin configuration register, all intermediate port states during switching of the pin direction and pin values are avoided.
12.3.1.2 Totem-pole with Pull-up In this mode, the configuration is as for totem-pole, expect the pin is configured with internal pull-up when set as input. Figure 12-4. I/O pin configuration - Totem-pole with pull-up (on input). 12.3.2 Bus-keeper In the bus-keeper configuration, it provides a weak bus-keeper that will keep the pin at its logic level when the pin is no longer driven to high or low.
12.3.3 Wired-OR In the wired-OR configuration, the pin will be driven high when the corresponding bits in the OUT and DIR registers are written to one. When the OUT register is set to zero, the pin is released, allowing the pin to be pulled low with the internal or an external pull-resistor. If internal pull-down is used, this is also active if the pin is set as input. Figure 12-6. Output configuration - Wired-OR with optional pull-down. 12.3.
12.4 Reading the Pin Value Independent of the pin data direction, the pin value can be read from the IN register, as shown in Figure 12-1 on page 127. If the digital input is disabled, the pin value cannot be read. The IN register bit and the preceding flip-flop constitute a synchronizer. The synchronizer introduces a delay on the internal signal line. Figure 12-8 on page 131 shows a timing diagram of the synchronization when reading an externally applied pin value.
12.5 Input Sense Configuration Input sensing is used to detect an edge or level on the I/O pin input. The different sense configurations that are available for each pin are detection of a rising edge, falling edge, or any edge or detection of a low level. High level can be detected by using the inverted input configuration. Input sensing can be used to trigger interrupt requests (IREQ) or events when there is a change on the pin. The I/O pins support synchronous and asynchronous input sensing.
Table 12-1. Synchronous sense support. Sense Settings Supported Interrupt Description Rising edge Yes Always triggered Falling edge Yes Always triggered Any edge Yes Always triggered Low level Yes Pin level must be kept unchanged during wake up Table 12-2. Full asynchronous sense support.
12.8 Alternate Port Functions Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When an alternate function is enabled, it might override the normal port pin function or pin value. This happens when other peripherals that require pins are enabled or configured to use pins. If and how a peripheral will override and use pins is described in the section for that peripheral. The port override signals and related logic (grey) are shown in Figure 12-10 on page 134.
12.9 Clock and Event Output It is possible to output the peripheral clock and event channel 0 events to a pin. This can be used to clock, control, and synchronize external functions and hardware to internal device timing. The output port pin is selectable. If an event occurs, it remains visible on the port pin as long as the event lasts; normally one peripheral clock cycle. 12.
12.12 Register Descriptions – Ports 12.12.1 DIR – Data Direction register Bit 7 6 5 4 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 +0x00 DIR[7:0] Bit 7:0 – DIR[7:0]: Data Direction This register sets the data direction for the individual pins of the port. If DIRn is written to one, pin n is configured as an output pin. If DIRn is written to zero, pin n is configured as an input pin. 12.12.
12.12.4 DIRTGL – Data Direction Toggle register Bit 7 6 5 4 +0x03 3 2 1 0 DIRTGL[7:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:0 – DIRTGL[7:0]: Port Data Direction Toggle This register can be used instead of a read-modify-write to toggle the direction of individual pins. Writing a one to a bit will toggle the corresponding bit in the DIR register. Reading this register will return the value of the DIR register. 12.12.
12.12.8 OUTTGL – Data Output Value Toggle register Bit 7 6 5 4 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 +0x07 OUTTGL[7:0] Bit 7:0 – OUTTGL[7:0]: Port Data Output Value Toggle This register can be used instead of a read-modify-write to toggle the output value of individual pins. Writing a one to a bit will toggle the corresponding bit in the OUT register. Reading this register will return the value in the OUT register. 12.12.
12.12.11INT0MASK – Interrupt 0 Mask register Bit 7 6 5 +0x0A 4 3 2 1 0 INT0MSK[7:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:0 – INT0MSK[7:0]: Interrupt 0 Mask bits These bits are used to mask which pins can be used as sources for port interrupt 0. If INT0MASKn is written to one, pin n is used as source for port interrupt 0.The input sense configuration for each pin is decided by the PINnCTRL registers. 12.12.
12.12.14REMAP – Pin Remap register The pin remap functionality is available for PORTC - PORTF only. Bit 7 6 5 4 3 2 1 0 +0x0E – – SPI USART0 TC0D TC0C TC0B TC0A Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
12.12.15PINnCTRL – Pin n Configuration Register Bit 7 6 – INVEN Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 5 4 3 2 1 OPC[2:0] 0 ISC[2:0] Bit 7 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. Bit 6 – INVEN: Inverted I/O Enable Setting this bit will enable inverted output and input data on pin n.
Note: ISC[2:0] Group Configuration 100 – Reserved 101 – Reserved 110 – Reserved 111 INTPUT_DISABLE 1. 2. Description Digital input buffer disabled(2) A low-level pin value will not generate events, and a high-level pin value will continuously generate events. Only PORTA - PORTF support the input buffer disable option. If the pin is used for analog functionality, such as AC or ADC, it is recommended to configure the pin to INPUT_DISABLE.
12.13 Register Descriptions – Port Configuration 12.13.1 MPCMASK – Multi-pin Configuration Mask register Bit 7 6 5 4 Read/Write R/W R/W R/W R/W Initial Value 0 0 0 0 +0x00 3 2 1 0 R/W R/W R/W R/W 0 0 0 0 MPCMASK[7:0] Bit 7:0 – MPCMASK[7:0]: Multi-pin Configuration Mask The MPCMASK register enables configuration of several pins of a port at the same time. Writing a one to bit n makes pin n part of the multi-pin configuration.
Bit 3:0 – VP2MAP: Virtual Port 2 Mapping These bits decide which ports should be mapped to Virtual Port 2. The registers DIR, OUT, IN, and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing the actual port registers. See Table 12-7 on page 144 for configuration. Table 12-7.
Table 12-8 on page 145 shows the possible configurations. Table 12-8. Event output pin selection. EVOUT[1:0] Group Configuration Description 00 OFF 01 PC Event channel 0 output on PORTC 10 PD Event channel 0 output on PORTD 11 PE Event channel 0 output on PORTE Event output disabled Bits 3:2 – CLKOUTSEL[1:0] : Clock Output Select These bits are used to select which of the peripheral clocks will be output to the port pin if CLKOUT is configured. Table 12-9. Clock output clock selection.
12.13.5 EVCTRL – Event Control register Bit 7 6 5 4 3 +0x06 – – – – – Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 2 1 0 EVOUTSEL[2:0] Bit 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. Bit 2:0 – EVOUTSEL[2:0]: Event Channel Output Selection These bits define which channel from the event system is output to the port pin.
12.14 Register Descriptions – Virtual Port 12.14.1 DIR – Data Direction register Bit 7 6 5 4 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 +0x00 DIR[7:0] Bit 7:0 – DIR[7:0]: Data Direction This register sets the data direction for the individual pins in the port mapped by VPCTRLA, virtual port-map control register A or VPCTRLB, virtual port-map control register B.
12.14.4 INTFLAGS – Interrupt Flag register Bit 7 6 5 4 3 2 1 0 +0x03 – – – – – – INT1IF INT0IF Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
12.
12.
13. TC0/1 – 16-bit Timer/Counter Type 0 and 1 13.
Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and highside output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It can also generate a synchronized bit pattern across the port pins.
Block Diagram Figure 13-2 on page 153 shows a detailed block diagram of the timer/counter without the extensions. Figure 13-2. Timer/counter block diagram. Base Counter BV PERBUF CTRLA PER CTRLD Clock Select Event Select "count" "clear" "load" "direction" Counter CNT OVF/UNF (INT/DMA Req.) Control Logic ERRIF (INT Req.) = =0 TOP BOTTOM "ev" UPDATE 13.3 Compare/Capture (Unit x = {A,B,C,D}) BV CCBUFx Control Logic CCx = Waveform Generation "match" OCx Out CCxIF (INT/DMA Req.
13.4 Clock and Event Sources The timer/counter can be clocked from the peripheral clock (clkPER) or the event system, and Figure 13-3 shows the clock and event selection. Figure 13-3. Clock and event selection. clkPER Common Prescaler clkPER / 2{0,...,15} clkPER / {1,2,4,8,64,256,1024} Event System events event channels CKSEL Control Logic EVSEL CNT EVACT (Encoding) The peripheral clock is fed into a common prescaler (common for all timer/counters in a device).
Figure 13-4. Period and compare double buffering. "write enable" BV UPDATE "data write" EN CCxBUF EN CCx CNT = "match" When the CC channels are used for a capture operation, a similar double buffering mechanism is used, but in this case the buffer valid flag is set on the capture event, as shown in Figure 13-5. For capture, the buffer register and the corresponding CCx register act like a FIFO. When the CC register is empty or read, any content in the buffer register is passed to the CC register.
Figure 13-6. Normal operation. CNT written MAX "update" TOP CNT BOTTOM DIR As shown in Figure 13-6, it is possible to change the counter value when the counter is running. The write access has higher priority than count, clear, or reload, and will be immediate. The direction of the counter can also be changed during normal operation. Normal operation must be used when using the counter as timer base for the capture channels. 13.6.
A counter wraparound can occur in any mode of operation when up-counting without buffering, as shown in Figure 13-8. This due to the fact that CNT and PER are continuously compared, and if a new TOP value that is lower than current CNT is written to PER, it will wrap before a compare match happen. Figure 13-8. Unbuffered dual-slope operation.
Figure 13-10.Event source selection for capture operation. Event System CH0MUX CH1MUX CCA capture Event channel 0 Event channel 1 CCB capture CCC capture CHnMUX Event channel n Rotate CCD capture Event Source Selection The event action setting in the timer/counter will determine the type of capture that is done. The CC channels must be enabled individually before capture can be done.
Figure 13-12 on page 159 shows an example where the period of an external signal is measured twice. Figure 13-12.Frequency capture of an external signal. Period (T) external signal events MAX "capture" CNT BOTTOM Since all capture channels use the same counter (CNT), only one capture channel must be enabled at a time. If two capture channels are used with different sources, the counter will be restarted on positive edge events from both input sources, and the result will have no meaning. 13.7.
13.7.4 32-bit Input Capture Two timer/counters can be used together to enable true 32-bit input capture. In a typical 32-bit input capture setup, the overflow event of the least-significant timer is connected via the event system and used as the clock input for the mostsignificant timer. The most-significant timer will be updated one peripheral clock period after an overflow occurs for the least-significant timer.
Figure 13-14.Frequency waveform generation. Period (T) Direction Change CNT written MAX "update" CNT TOP BOTTOM WG Output The waveform frequency (fFRQ) is defined by the following equation: fclk PER f FRQ = ---------------------------------2N CCA + 1 where N represents the prescaler divider used. The waveform generated will have a maximum frequency of half of the peripheral clock frequency (fclkPER) when CCA is set to zero (0x0000) and no prescaling is used.
fclk PER f PWM_SS = ----------------------------N PER + 1 where N represents the prescaler divider used. The waveform generated will have a maximum frequency of half of the peripheral clock frequency (fclkPER) when CCA is set to zero (0x0000) and no prescaling is used. This also applies when using the hi-res extension, since this increases the resolution and not the frequency. 13.8.
Figure 13-17 on page 163 shows the port override for a timer/counter. The timer/counter CC channel will override the port pin output value (OUT) on the corresponding port pin. Enabling inverted I/O on the port pin (INVEN) inverts the corresponding WG output. Figure 13-17.Port override for timer/counter 0 and 1. OUT OCx Waveform CCExEN 13.9 INVEN Interrupts and events The timer/counter can generate both interrupts and events.
13.12 Register Description 13.12.1 CTRLA – Control register A Bit 7 6 5 4 +0x00 – – – – Read/Write R R R R R/W Initial Value 0 0 0 0 0 3 2 1 0 R/W R/W R/W 0 0 0 CLKSEL[3:0] Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. Bit 3:0 – CLKSEL[3:0]: Clock Select These bits select the clock source for the timer/counter according to Table 13-3.
Bit 3 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. Bit 2:0 – WGMODE[2:0]: Waveform Generation Mode These bits select the waveform generation mode, and control the counting sequence of the counter, TOP value, UPDATE condition, interrupt/event condition, and type of waveform that is generated according to Table 13-4. No waveform generation is performed in the normal mode of operation.
13.12.4 CTRLD – Control register D Bit 7 6 +0x03 5 4 EVACT[2:0] 3 2 EVDLY 1 0 EVSEL[3:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:5 – EVACT[2:0]: Event Action These bits define the event action the timer will perform on an event according to Table 13-5 on page 166. The EVSEL setting will decide which event source or sources have control in this case. Table 13-5. Timer event action selection.
EVSEL[3:0] Group Configuration Event Source 0100 – Reserved 0101 – Reserved 0110 – Reserved 0111 – Reserved 1nnn CHn Event channel n, n={0,...,7} 13.12.5 CTRLE – Control register E Bit 7 6 5 4 3 2 +0x04 – – – – – – Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 1 0 BYTEM[1:0] Bit 7:2 – Reserved These bits are unused and reserved for future use.
Bit 3:2 – ERRINTLVL[1:0]:Timer Error Interrupt Level These bits enable the timer error interrupt and select the interrupt level as described in “Interrupts and Programmable Multilevel Interrupt Controller” on page 118. Bit 1:0 – OVFINTLVL[1:0]:Timer Overflow/Underflow Interrupt Level These bits enable the timer overflow/underflow interrupt and select the interrupt level as described in “Interrupts and Programmable Multilevel Interrupt Controller” on page 118. 13.12.
Table 13-8. Command selections CMD Group Configuration Command Action 00 NONE 01 UPDATE Force update 10 RESTART Force restart 11 RESET None Force hard reset (ignored if T/C is not in OFFstate) Bit 1 – LUPD: Lock Update When this bit is set, no update of the buffered registers is performed, even though an UPDATE condition has occurred. Locking the update ensures that all buffers, including DTI buffers, are valid before an update is performed.
13.12.10INTFLAGS – Interrupt Flag register Bit 7 6 5 4 3 2 1 0 CCDIF CCCIF CCBIF CCAIF – – ERRIF OVFIF Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 +0x0C Bit 7:4 – CCxIF: Compare or Capture Channel x Interrupt Flag The compare or capture interrupt flag (CCxIF) is set on a compare match or on an input capture event on the corresponding CC channel.
13.12.11TEMP – Temporary bits for 16-bit Access The TEMP register is used for single-cycle, 16-bit access to the 16-bit timer/counter registers by the CPU. The DMA controller has a separate temporary storage register. There is one common TEMP register for all the 16-bit Timer/counter registers. For more details, refer to “Accessing 16-bit Registers” on page 13. Bit 7 6 5 4 +0x0F 3 2 1 0 TEMP[7:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 13.12.
13.12.15PERH – Period register High Bit 7 6 5 4 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 1 1 1 1 +0x27 PER[15:8] Bit 7:0 – PER[15:8]: Period high byte These bits hold the MSB of the 16-bit period register. 13.12.16CCxL – Compare or Capture x register Low The CCxH and CCxL register pair represents the 16-bit value, CCx. These 16-bit register pairs have two functions, depending of the mode of operation.
13.12.18PERBUFL – Timer/Counter Period Buffer Low The PERBUFH and PERBUFL register pair represents the 16-bit value, PERBUF. This 16-bit register serves as the buffer for the period register (PER). Accessing this register using the CPU or DMA will affect the PERBUFV flag.
13.12.21CCxBUFH – Compare or Capture x Buffer register High Bit 7 6 5 4 3 2 1 0 CCxBUF[15:8] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:0 – CCxBUF[15:8]: Compare or Capture Buffer high byte These bits hold the MSB of the 16-bit compare or capture buffer register.
13.
14. TC2 – 16-bit Timer/Counter Type 2 14.
14.3 Block Diagram Figure 14-1. Block diagram of the 16-bit timer/counter 0 with split mode. Base Counter HPER "count high" "load high" "count low" "load low" Counter HCNT Clock Select CTRLA LPER LCNT HUNF (INT/DMA Req.) Control Logic LUNF (INT/DMA Req.) =0 BOTTOML BOTTOMH =0 Compare (Unit x = {A,B,C,D}) LCMPx Waveform Generation OCLx Out LCMPx "match" = (INT/DMA Req.) Compare (Unit x = {A,B,C,D}) HCMPx = 14.
The peripheral clock (clkPER) is fed into the common prescaler (common for all timer/counters in a device). A selection of prescaler outputs from 1 to 1/1024 is directly available. In addition, the whole range of time prescalings from 1 to 215 is available through the event system. The clock selection (CLKSEL) selects one of the clock prescaler outputs or an event channel for the high-byte counter (HCNT) and low-byte counter (LCNT).
14.6.1 Waveform Generation The compare channels can be used for waveform generation on the corresponding port pins. To make the waveform visible on the connected port pin, the following requirements must be fulfilled: 1. The compare channels to be used must be enabled. This will override the corresponding port pin output register. 2. The direction for the associated port pin must be set to output. Inverted waveform output can be achieved by setting invert I/O on the port pin.
Figure 14-6. Port override for low- and high-byte timer/counters. OUT OCx Waveform LCMPENx / HCMPENx 14.7 INVEN Interrupts and Events The timer/counters can generate interrupts and events. The counter can generate an interrupt on underflow, and each CMP channel for the low-byte counter has a separate compare interrupt. Events will be generated for all conditions that can generate interrupts. For details on event generation and available events, refer to “Event System” on page 65. 14.
14.10 Register Description 14.10.1 CTRLA – Control register A Bit 7 6 5 4 3 2 1 0 +0x00 – – – – Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 CLKSEL[3:0] Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. Bit 3:0 – CLKSEL[3:0]: Clock Select These bits select clock source for the timer/counter according to Table 14-2.
14.10.3 CTRLC – Control register C Bit 7 6 5 4 3 2 1 0 HCMPD HCMPC HCMPB HCMPA LCMPD LCMPC LCMPB LCMPA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 +0x02 Bit 7:0 – HCMPx/LCMPx: High/Low Compare x Output Value These bits allow direct access to the waveform generator's output compare value when the timer/counter is OFF. This is used to set or clear the WG output value when the timer/counter is not running. 14.10.
14.10.5 INTCTRLA – Interrupt Enable register A Bit 7 6 5 4 +0x06 – – – – HUNFINTLVL[1:0] Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 3 2 1 0 LUNFINTLVL[1:0] Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Table 14-4. Command selections. CMD Group Configuration 00 NONE 01 — 10 RESTART 11 RESET Description None Reserved Force restart Force hard reset (ignored if T/C is not in OFF state) Bit 1:0 – CMDEN[1:0]: Command Enable These bits are used to indicate for which timer/counter the command (CMD) is valid. Table 14-5. Command enable selections.
14.10.9 LCNT – Low-byte Count register Bit 7 6 5 4 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 +0x20 LCNT[7:0] Bit 7:0 – LCNT[7:0] LCNT contains the eight-bit counter value for the low-byte timer/counter. The CPU and DMA write accesses have priority over count, clear, or reload of the counter. 14.10.
14.10.13LCMPx – Low-byte Compare register x Bit 7 6 5 4 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 LCMPx[7:0] Bit 7:0 – LCMPx[7:0], x=[A, B, C, D] LCMPx contains the eight-bit compare value for the low-byte timer/counter. These registers are all continuously compared to the counter value. Normally, the outputs from the comparators are then used for generating waveforms. 14.10.
14.
15. AWeX – Advanced Waveform Extension 15.
time insertion between LS and HS switching. The DTI output will override the normal port value according to the port override setting. Refer to “I/O Ports” on page 126 for more details. The pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition, the WG output from compare channel A can be distributed to and override all the port pins. When the pattern generator unit is enabled, the DTI unit is bypassed.
Figure 15-2. Timer/counter extensions and port override logic.
dead time. The high side and low side have independent dead-time setting, and the dead-time registers are double buffered. Figure 15-3. Dead-time generator block diagram. BV DTLSBUF BV DTHSBUF DTHS DTLS Dead Time Generator LOAD EN Counter =0 "DTLS" WG output D Q (To PORT) "DTHS" Edge Detect (To PORT) As shown in Figure 15-4 on page 191, the 8-bit dead-time counter is decremented by one for each peripheral clock cycle, until it reaches zero.
Figure 15-5. Pattern generator block diagram. Timer/Counter 0 (TCx0) UPDATE BV DTLSBUF EN OUTOVEN BV CCA WG output 1 to 8 Expand DTHSBUF EN OUTx Px[7:0] As with the other timer/counter double buffered registers, the register update is synchronized to the UPDATE condition set by the waveform generation mode. If the synchronization provided is not required by the application, the application code can simply access the DTIOE and PORTx registers directly.
When returning from a fault state the DIR[7:0] bits corresponding to the enabled DTI channels are restored. OUTOVEN is unaffected by the fault except that writing to the register from software is blocked. The UPDATE condition used to restore normal operation is the same as the one in the timer/counter. 15.6.
15.7 Register Description 15.7.1 CTRL – Control register Bit 7 6 5 4 3 2 1 0 +0x00 – – PGM CWCM DTICCDEN DTICCCEN DTICCBEN DTICCAEN Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. Bit 5 – PGM: Pattern Generation Mode Setting this bit enables the pattern generation mode.
15.7.3 FDCTRL - Fault Detection Control register Bit 7 6 5 4 3 2 +0x03 – – – FDDBD – FDMODE Read/Write R R R R/W R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 1 0 FDACT[1:0] Bit 7:5 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
15.7.4 STATUS – Status register Bit 7 6 5 4 3 2 1 0 +0x04 – – – – – FDF DTHSBUFV DTLSBUFV Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. Bit 2 – FDF: Fault Detect Flag This flag is set when a fault detect condition is detected; i.e.
15.7.7 DTLS – Dead-time Low Side register Bit 7 6 5 4 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 3 2 1 0 +0x08 DTLS[7:0] Bit 7:0 – DTLS: Dead-time Low Side This register holds the number of peripheral clock cycles for the dead-time low side. 15.7.
15.7.11 OUTOVEN – Output Override Enable register Bit 7 6 5 4 Read/Write R/W(1) R/W(1) R/W(1) R/W(1) Initial Value 0 0 0 0 +0x0C Note: 3 2 1 0 R/W(1) R/W(1) R/W(1) R/W(1) 0 0 0 0 OUTOVEN[7:0] 1. Can be written only if the fault detect flag (FDF) is zero. Bit 7:0 – OUTOVEN[7:0]: Output Override Enable These bits enable override of the corresponding port output register (i.e., one-to-one bit relation to pin position). The port direction is not overridden. 15.
16. Hi-Res – High-Resolution Extension 16.1 Features Increases waveform generator resolution up to 8x (3 bits) Supports frequency, single-slope PWM, and dual-slope PWM generation Supports the AWeX when this is used for the same timer/counter 16.2 Overview The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a timer/counter by four or eight.
16.3 Register Description 16.3.1 CTRLA – Control register A Bit 7 6 5 4 3 2 +0x00 – – – – – HRPLUS Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 1 0 HREN[1:0] Bit 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. Bit 2 – HRPLUS: High Resolution Plus Setting this bit enables high resolution plus.
17. RTC – Real-Time Counter 17.1 Features 16-bit resolution Selectable clock source 32.768kHz external crystal External clock 32.768kHz internal oscillator 32kHz internal ULP oscillator Programmable 10-bit clock prescaling One compare register One period register Clear counter on period overflow Optional interrupt/event on overflow and compare match 17.
17.2.1 Clock Domains The RTC is asynchronous, operating from a different clock source independently of the main system clock and its derivative clocks, such as the peripheral clock. For control and count register updates, it will take a number of RTC clock and/or peripheral clock cycles before an updated register value is available in a register or until a configuration change has effect on the RTC. This synchronization time is described for each register.
17.3 Register Descriptions 17.3.1 CTRL – Control register Bit 7 6 5 4 3 2 1 0 +0x00 – – – – – Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PRESCALER[2:0] Bit 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
17.3.3 INTCTRL – Interrupt Control register Bit 7 6 5 4 +0x02 – – – – COMPINTLVL[1:0] Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 3 2 1 0 OVFINTLVL[1:0] Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
17.3.5 TEMP – Temporary register Bit 7 6 5 4 +0x04 3 2 1 0 TEMP[7:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:0 – TEMP[7:0]: Temporary bits This register is used for 16-bit access to the counter value, compare value, and TOP value registers. The low byte of the 16-bit register is stored here when it is written by the CPU. The high byte of the 16-bit register is stored when the low byte is read by the CPU.
17.3.8 PERL – Period register Low The PERH and PERL register pair represents the 16-bit value, PER. PER is constantly compared with the counter value (CNT). A match will set OVFIF in the INTFLAGS register and clear CNT. Reading and writing 16-bit values requires special attention. Refer to “Accessing 16-bit Registers” on page 13 for details. Due to synchronization between the RTC clock and system clock domains, there is a latency of two RTC clock cycles from updating the register until this has an effect.
17.3.11 COMPH – Compare register High 7 Bit 6 5 4 +0x0D 3 2 1 0 COMP[15:8] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:0 – COMP[15:8]: Compare value high byte These bits hold the MSB of the 16-bit RTC compare value.
17.4 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 +0x00 +0x01 +0x02 +0x03 +0x04 +0x08 +0x09 +0x0A +0x0B +0x0C +0x0D CTRL STATUS INTCTRL INTFLAGS TEMP CNTL CNTH PERL PERH COMPL COMPH – – – – – – – – – – – – – – – – 17.
18. USB – Universal Serial Bus Interface 18.1 Features USB 2.0 full speed (12Mbps) and low speed (1.
Multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as multiple packets without software intervention. This reduces the CPU intervention and the interrupts needed for USB transfers. For low-power operation, the USB module can put the microcontroller into any sleep mode when the USB bus is idle and a suspend condition is given. Upon bus resumes, the USB module can wake up the microcontroller from any sleep mode. Figure 18-1.
18.3.1 Start of Frame When a start of frame (SOF) token is detected and storing of the frame numbers is enabled, the frame number from the token is stored in the frame number register (FRAMENUM) and the start of frame interrupt flag (SOFIF) in the interrupt flag B clear/set register (INTFLAGSBCLR/SET) is set. If there was a CRC or bit-stuff error, the frame error (FRAMEERR) flag in FRAMENUM is set. 18.3.
Figure 18-4. OUT transaction.
When an OUT token is detected and the device address of the token packet does not match that of the endpoint, the packet is discarded and the USB module returns to idle and waits for the next token packet. 18.3.4 IN If an IN token is detected the, the USB module fetches the endpoint CTRL and STATUS register data from the addressed input endpoint in the endpoint configuration table. If the endpoint is disabled, the USB module returns to idle and waits for the next token packet.
18.4 SRAM Memory Mapping The USB module uses internal SRAM to store the: Endpoint configuration table USB frame number Transaction complete FIFO The endpoint pointer register (EPPTR) is used to set the SRAM address for the endpoint configuration table. The USB frame number (FRAMENUM) and transaction complete FIFO (FIFO) locations are derived from this. The locations of these areas are selectable inside the internal SRAM. Figure on page 214 gives the relative memory location of each area.
Figure 18-7. Clock generation configuration. USBSRC 48MHz full speed USB module 6MHz for low speed USB clock prescaler PLL 48MHz Internal Oscillator USBPSDIV 18.6 Ping-pong Operation When an endpoint is configured for ping-pong operation, it uses the input and output data buffers to create a single, double-buffered endpoint that can be set to input or output direction.
18.7 Multipacket Transfers Multipacket transfer enables a data payload exceeding the maximum data payload size of an endpoint to be transferred as multiple packets without any software intervention. This reduces interrupts and software intervention to the higher level USB transfer, and frees up significant CPU time. Multipacket transfer is identical to the IN and OUT transactions described above, unless otherwise noted in this section.
18.8 Auto Zero Length Packet Some IN transfer requires a zero length packet to be generated in order to signal end of transfer to the host. The auto zero length packet (AZLP) function can be enabled to perform this generation automatically, thus removing the need for application software or CPU intervention to perform this task. 18.
18.10 Interrupts and Events The USB module can generate interrupts and events. The module has 10 interrupt sources. These are split between two interrupt vectors, the transaction complete (TRNCOMPL) interrupt and the bus event (BUSEVENT) interrupt. An interrupt group is enabled by setting its interrupt level (INTLVL), while different interrupt sources are enabled individually or in groups.
Table 18-1. Transaction complete interrupt sources. Interrupt source Description Transfer complete (TRNIF) An IN or OUT transaction is completed Setup complete (SETUPIF) A SETUP transaction is completed 18.10.2 Bus Event Interrupt The bus event (BUSEVENT) interrupt is used for all interrupts that signal various types of USB line events or error conditions. These interrupts are related to the USB lines, and are generated for the USB module and per endpoint.
18.12 On-chip Debug When a break point is reached during on-chip debug (OCD) sessions, the CPU clock can be below 12MHz. If this happens, the USB module will behave as follows: USB OCD break mode disabled: The USB module immediately acknowledges any OCD break request. The USB module will not be able to follow up on transactions received from the USB host, and its behaviour from the host point of view is not predictable.
18.13 Register Description – USB 18.13.1 CTRLA – Control register A Bit +0x00 7 6 5 4 3 2 1 0 ENABLE SPEED FIFOEN STFRNUM Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 MAXEP[3:0] Bit 7 – ENABLE: USB Enable Setting this bit enables the USB interface. Clearing this bit disables the USB interface and immediately aborts any ongoing transactions. Bit 6 – SPEED: Speed Select This bit selects between low and full speed operation.
Bit 2 – RWAKEUP: Remote Wake-up Setting this bit sends an upstream resume on the USB lines if the bus is in the suspend state for at least 5 ms. Bit 1 – GNACK: Global NACK When this bit is set, the USB module will NACK all incoming transactions. Expect for a SETUP packet, this prevents the USB module from performing any on-chip SRAM access, giving all SRAM bandwidth to the CPU and/or DMA controller.
18.13.5 FIFOWP – FIFO Write Pointer register Bit 7 6 5 +0x04 – – – Read/Write R R R R/W R/W Initial Value 0 0 0 0 0 4 3 2 1 0 R/W R/W R/W 0 0 0 FIFOWP[4:0] Bit 7:5 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. Bit 4:0 – FIFOWP[4:0]: FIFO Write Pointer These bits contain the transaction complete FIFO write pointer.
18.13.8 EPPTRH – Endpoint Configuration Table Pointer High Bit 7 6 5 4 +0x07 3 2 1 0 EPPTR[15:8] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:0 – EPPTR[15:8]: Endpoint Configuration Table Pointer high byte This register contains the eight msbs of the endpoint configuration table pointer (EPPTR). 18.13.
Bit 3:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. Bit 1:0 – INTLVL[1:0]: Interrupt Level These bits enable the USB interrupts and select the interrupt level, as described in “Interrupts and Programmable Multilevel Interrupt Controller” on page 118. In addition, each USB interrupt source must be separately enabled. 18.13.
Bit 3 – CRCIF: Isochronous CRC Error Interrupt Flag This flag is set when a CRC error has been detected in an incoming data packet to an isochronous endpoint. Bit 2 – UNFIF: Underflow Interrupt Flag This flag is set when the addressed endpoint in an IN transaction does not have data to send to the host. Bit 1 – OVFIF: Overflow Interrupt Flag This flag is set when the addressed endpoint in an OUT transaction is not ready to accept data from the host.
18.13.14CALH – Calibration register High Bit 7 6 5 4 +0x3B 3 2 1 0 CAL[15:8] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:0 – CAL[15:8]: PAD Calibration high byte This byte holds the eight msbs of CAL.
18.14 Register Description – USB Endpoint Each of the 16 endpoint addresses have one input and one output endpoint. Each endpoint has eight bytes of configuration/status data located in internal SRAM. The address to the first configuration byte is (EPPTR[15:0] + 16 × endpoint address) for output endpoints and (EPPTR[15:0] + 16 × endpoint address + 8) for input endpoints.
Bit 1 – BUSNACK0: Data Buffer 0 Not Acknowledge Flag When this flag is set, the USB module will discard incoming data to data buffer 0 in an OUT transaction, and will not return any data from data buffer 0 in an IN transaction. For control, bulk, and interrupt endpoints, a NAK handshake is returned. This flag is cleared by writing a one to its bit location.
Bit 2 – STALL: Endpoint STALL This bit controls the STALL behavior if the endpoint. Bit 1:0 – BUFSIZE[1:0]: Data Size These bits configure the maximum data payload size for the endpoint. Incoming data bytes exceeding the maximum data payload size are discarded. Bit 2:0 – BUFSIZE[2:0]: Data Size These bits configure the maximum data payload size for the endpoint when configured for isochronous operation. Table 18-5.
18.14.4 CNTH – Counter High register Bit 7 6 5 4 3 2 AZLP – – – – – Read/Write R/W R R R R R R/W R/W Initial Value X X X X X X X X +0x03 1 0 CNT[9:8] Bit 6 – AZLP: Automatic Zero Length Packet When this bit is set, the USB module will manage the ZLP handshake by hardware. This applies to IN endpoints only. When this bit is zero, the ZLP handshake must be managed by firmware. Bit 6:2 – Reserved These bits are unused and reserved for future use.
18.14.7 AUXDATAL – Auxiliary Data Low register The AUXDATAL and AUXDATAH registers represent the 16-bit value, AUXDATA, that is used for multipacket transfers. For IN endpoints, AUXDATA holds the total number of bytes sent. AUXDATA should be written to zero when setting up a new transfer. For OUT endpoints, AUXDATA holds the total data size for the complete transfer. This value must be a multiple of the maximum packet size, except for ISO 1023-byte endpoints.
18.15 Register Description - Frame 18.15.1 FRAMENUML – Frame Number Low register The FRAMENUML and FRAMENUMH registers represent the 11-bit value, FRAMENUM, that holds the frame number from the most recently received start of frame packet. Bit 7 6 5 +0x00 4 3 2 1 0 FRAMENUM[7:0] Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 2 1 0 Bit 7:0 – FRAMENUM[7:0]: Frame Number This byte contains the eight lsbs of the frame number (FRAMENUM). 18.15.
18.
19. TWI – Two-Wire Interface 19.
19.3 General TWI Bus Concepts The TWI provides a simple, bidirectional, two-wire communication bus consisting of a serial clock line (SCL) and a serial data line (SDA). The two lines are open-collector lines (wired-AND), and pull-up resistors (Rp) are the only external components needed to drive the bus.
Figure 19-2. Basic TWI transaction diagram topology for a 7-bit address bus . SDA SCL 6 ... 0 S ADDRESS S ADDRESS 7 ... 0 R/W R/W ACK A DATA DATA 7 ...
Figure 19-4. Data validity. SDA SCL DATA Valid Change Allowed Combining bit transfers results in the formation of address and data packets. These packets consist of eight data bits (one byte) with the most-significant bit transferred first, plus a single-bit not-acknowledge (NACK) or acknowledge (ACK) response. The addressed device signals ACK by pulling the SCL line low during the ninth clock cycle, and signals NACK by leaving the line SCL high. 19.3.
transferred. If the slave signals a NACK to the data, the master must assume that the slave cannot receive any more data and terminate the transaction. Figure 19-6 on page 239 illustrates the master read transaction. The master initiates the transaction by issuing a START condition followed by an address packet with the direction bit set to one (ADDRESS+R). The addressed slave must acknowledge the address for the master to be allowed to continue the transaction. Figure 19-6. Master read transaction.
the master and slave device can randomly stretch the clock on a byte level basis before and after the ACK/NACK bit. This provides time to process incoming or prepare outgoing data, or perform other time-critical tasks. In the case where the slave is stretching the clock, the master will be forced into a wait state until the slave is ready, and vice versa. 19.3.8 Arbitration A master can start a bus transaction only if it has detected that the bus is idle.
Figure 19-10.Clock synchronization. Low Period Count Wait State High Period Count DEVICE1_SCL DEVICE2_SCL SCL (wired-AND) A high-to-low transition on the SCL line will force the line low for all masters on the bus, and they will start timing their low clock period. The timing length of the low clock period can vary among the masters. When a master (DEVICE1 in this case) has completed its low period, it releases the SCL line. However, the SCL line will not go high until all masters have released it.
Figure 19-11.Bus state, state diagram. RESET UNKNOWN (0b00) P + Timeout S Sr IDLE BUSY P + Timeout (0b01) (0b11) Command P Arbitration Lost Write ADDRESS (S) OWNER (0b10) Write ADDRESS(Sr) After a system reset and/or TWI master enable, the bus state is unknown. The bus state machine can be forced to enter idle by writing to the bus state bits accordingly. If no state is set by application software, the bus state will become idle when the first STOP condition is detected.
Figure 19-12.TWI master operation.
19.5.1.4 Case M4: Address packet transmit complete - Direction bit set If the master receives an ACK from the slave, the master proceeds to receive the next byte of data from the slave. When the first data byte is received, the master read interrupt flag is set and the master received acknowledge flag is cleared. The clock hold is active at this point, preventing further activity on the bus. 19.5.
19.6.1 Receiving Address Packets When the TWI slave is properly configured, it will wait for a START condition to be detected. When this happens, the successive address byte will be received and checked by the address match logic, and the slave will ACK a correct address and store the address in the DATA register. If the received address is not a match, the slave will not acknowledge and store address, and will wait for a new START condition.
19.8 Register Description – TWI 19.8.1 CTRL – Common Control Register Bit 7 6 5 4 3 2 1 0 +0x00 – – – – – Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SDAHOLD[1:0] EDIEN Bit 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. Bit 2:1 – SDAHOLD[1:0]: SDA Hold Time Enable.
19.9 Register Description – TWI Master 19.9.1 CTRLA – Control register A Bit 7 +0x00 6 5 4 3 2 1 0 RIEN WIEN ENABLE – – – Read/Write R/W R/W R/W R/W R/W R R R Initial Value 0 0 0 0 0 0 0 0 INTLVL[1:0] Bit 7:6 – INTLVL[1:0]: Interrupt Level These bits select the interrupt level for the TWI master interrupt, as described in “Interrupts and Programmable Multilevel Interrupt Controller” on page 118.
Table 19-3. TWI master inactive bus timeout settings. TIMEOUT[1:0] Group Configuration Description 00 DISABLED 01 50US 50μs, normally used for SMBus at 100kHz 10 100US 100μs 11 200US 200μs Disabled, normally used for I2C Bit 1 – QCEN: Quick Command Enable When quick command is enabled, the corresponding interrupt flag is set immediately after the slave acknowledges the address (read or write interrupt). At this point, software can issue either a STOP or a repeated START condition.
Table 19-5. CMD bit description. CMD[1:0] Group Configuration MODE Operation 00 NOACT X Reserved 01 START X Execute acknowledge action succeeded by repeated START condition W No operation R Execute acknowledge action succeeded by a byte receive X Execute acknowledge action succeeded by issuing a STOP condition 10 BYTEREC 11 STOP Writing a command to the CMD bits will clear the master interrupt flags and the CLKHOLD flag. 19.9.
Bit 4 – RXACK: Received Acknowledge This flag contains the most recently received acknowledge bit from the slave. This is a read-only flag. When read as zero, the most recent acknowledge bit from the slave was ACK, and when read as one the most recent acknowledge bit was NACK. Bit 3 – ARBLOST: Arbitration Lost This flag is set if arbitration is lost while transmitting a high data bit or a NACK bit, or while issuing a START or repeated START condition on the bus.
f sys - – 5 [2] BAUD = --------------2 f TWI The BAUD register should be written only while the master is disabled. 19.9.6 ADDR – Address register Bit 7 6 5 4 +0x05 3 2 1 0 ADDR[7:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 When the address (ADDR) register is written with a slave address and the R/W bit while the bus is idle, a START condition is issued and the 7-bit slave address and the R/W bit are transmitted on the bus.
19.10 Register Description – TWI Slave 19.10.1 CTRLA – Control register A Bit 7 +0x00 6 INTLVL[1:0] 5 4 3 2 1 0 DIEN APIEN ENABLE PIEN PMEN SMEN Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:6 – INTLVL[1:0]: Interrupt Level These bits select the interrupt level for the TWI master interrupt, as described in “Interrupts and Programmable Multilevel Interrupt Controller” on page 118.
Table 19-7. TWI slave acknowledge actions. ACKACT Action 0 Send ACK 1 Send NACK Bit 1:0 – CMD[1:0]: Command Writing these bits trigger the slave operation as defined by Table 19-8. The CMD bits are strobe bits and always read as zero. The operation is dependent on the slave interrupt flags, DIF and APIF. The acknowledge action is only executed when the slave receives data bytes or address byte from the master. Table 19-8. TWI slave command.
19.10.3 STATUS – Status register Bit 7 6 5 4 3 2 +0x02 DIF APIF CLKHOLD RXACK COLL BUSERR DIR AP Read/Write R/W R/W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 1 0 Bit 7 – DIF: Data Interrupt Flag This flag is set when a data byte is successfully received; i.e., no bus error or collision occurred during the operation. Writing a one to this bit location will clear DIF. When this flag is set, the slave forces the SCL line low, stretching the TWI clock period.
19.10.4 ADDR – Address register The TWI slave address register should be loaded with the 7-bit slave address (in the seven most significant bits of ADDR) to which the TWI will respond. The lsb of ADDR is used to enable recognition of the general call address (0x00).
19.10.6 ADDRMASK – Address Mask register Bit 7 6 5 Read/Write R/W R/W R/W Initial Value 0 0 0 +0x05 4 3 2 1 R/W R/W R/W R/W R/W 0 0 0 0 0 ADDRMASK[7:1] 0 ADDREN Bit 7:1 – ADDRMASK[7:1]: Address Mask These bits can act as a second address match register or as an address mask register, depending on the ADDREN setting. If ADDREN is set to zero, ADDRMASK can be loaded with a 7-bit slave address mask.
19.11 Register Summary - TWI Address Name Bit 7 Bit 6 Bit 5 +0x00 +0x01 +0x08 CTRL MASTER SLAVE – – – Bit 4 Bit 3 – – Offset address for TWI Master Offset address for TWI Slave Bit 2 Bit 1 SDAHOLD[1:0] Bit 0 Page EDIEN 246 Bit 0 Page 19.
20. SPI – Serial Peripheral Interface 20.1 Features Full-duplex, three-wire synchronous data transfer Master or slave operation Lsb first or msb first data transfer Eight programmable bit rates Interrupt flag at the end of transmission Write collision flag to indicate data collision Wake up from idle sleep mode Double speed master mode 20.2 Overview The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins.
Table 20-1. SPI pin override and directions. 20.3 Pin Master Mode Slave Mode MOSI User defined Input MISO Input User defined SCK User defined Input SS User defined Input Master Mode In master mode, the SPI interface has no automatic control of the SS line. If the SS pin is used, it must be configured as output and controlled by user software.
Figure 20-2. SPI transfer modes. Mode 0 Mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Mode 1 Mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) LSB first (DORD = 1) 20.
20.7 Register Description 20.7.1 CTRL – Control register Bit +0x00 7 6 5 4 3 2 1 CLK2X ENABLE DORD MASTER Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 MODE[1:0] 0 PRESCALER[1:0] Bit 7 – CLK2X: Clock Double When this bit is set, the SPI speed (SCK frequency) will be doubled in master mode (see Table 20-3 on page 262). Bit 6 – ENABLE: Enable Setting this bit enables the SPI module. This bit must be set to enable any SPI operations.
Table 20-3. Relationship between SCK and the peripheral clock (ClkPER) frequency. CLK2X PRESCALER[1:0] SCK Frequency 0 00 ClkPER/4 0 01 ClkPER/16 0 10 ClkPER/64 0 11 ClkPER/128 1 00 ClkPER/2 1 01 ClkPER/8 1 10 ClkPER/32 1 11 ClkPER/64 20.7.
20.7.4 DATA – Data register Bit 7 6 5 4 +0x03 3 2 1 0 DATA[7:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The DATA register is used for sending and receiving data. Writing to the register initiates the data transmission, and the byte written to the register will be shifted out on the SPI output line. Reading the register causes the shift register receive buffer to be read, returning the last byte successfully received. 20.
21. USART 21.
Figure 21-1. USART block diagram.
Figure 21-2. Clock generation logic, block diagram. BSEL Baud Rate Generator CLK2X fBAUD /2 /4 /2 0 1 0 fOSC 1 PORT_INV xcki XCK Pin txclk DDR_XCK Sync Register Edge Detector 0 UMSEL [1] 1 xcko 1 DDR_XCK 0 rxclk 21.3.1 Internal Clock Generation - The Fractional Baud Rate Generator The fractional baud rate generator is used for internal clock generation for asynchronous modes, synchronous master mode, and master SPI mode operation.
Note: 1. The baud rate is defined to be the transfer rate in bits per second (bps) For BSEL=0, all baud rates must be achieved by changing BSEL instead of setting BSCALE: BSEL = (2 BSCALE-1) BSCALE BSEL BSCALE BSEL 1 0 0 1 2 0 0 3 3 0 0 7 4 0 0 15 5 0 0 31 6 0 0 63 7 0 0 127 21.3.2 External Clock External clock (XCK) is used in synchronous slave mode operation.
Figure 21-3. Synchronous mode XCK timing. UCPOL = 1 XCK RxD / TxD Sample XCK UCPOL = 0 RxD / TxD Sample Using the inverted I/O (INVEN) setting for the corresponding XCK port pin, the XCK clock edges used for data sampling and data change can be selected. If inverted I/O is disabled (INVEN=0), data will be changed at the rising XCK clock edge and sampled at the falling XCK clock edge.
Figure 21-4. UCPHA and INVEN data transfer timing diagrams. UCPHA=0 UCPHA=1 UCPOL=0 21.4 UCPOL=1 XCK XCK Data setup (TXD) Data setup (TXD) Data sample (RXD) Data sample (RXD) XCK XCK Data setup (TXD) Data setup (TXD) Data sample (RXD) Data sample (RXD) Frame Formats Data transfer is frame based, where a serial frame consists of one character of data bits with synchronization bits (start and stop bits) and an optional parity bit for error checking.
21.4.2 SPI Frame Formats The serial frame in SPI mode is defined to be one character of eight data bits. The USART in master SPI mode has two selectable frame formats: 8-bit data, msb first 8-bit data, lsb first After a complete, 8-bit frame is transmitted, a new frame can directly follow it, or the communication line can return to the idle (high) state. 21.5 USART Initialization USART initialization should use the following sequence: 1.
21.7.1 Receiving Frames The receiver starts data reception when it detects a valid start bit. Each bit that follows the start bit will be sampled at the baud rate or XCK clock and shifted into the receive shift register until the first stop bit of a frame is received. A second stop bit will be ignored by the receiver. When the first stop bit is received and a complete serial frame is present in the receive shift register, the contents of the shift register will be moved into the receive buffer.
Figure 21-6. Start bit sampling. RxD Sample (U2X = 0) Sample (U2X = 1) IDLE 0 0 0 START 1 2 3 1 4 5 2 6 7 3 8 9 4 BIT 0 10 5 11 12 6 13 14 7 15 16 8 1 1 2 3 2 When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection sequence is initiated. Sample 1 denotes the first zero-sample, as shown in the figure.
21.8.3 Asynchronous Operational Range The operational range of the receiver is dependent on the mismatch between the received bit rate and the internally generated baud rate. If an external transmitter is sending using bit rates that are too fast or too slow, or if the internally generated baud rate of the receiver does not match the external source’s base frequency, the receiver will not be able to synchronize the frames to the start bit.
D #(Data + Parity Bit) Rslow [%] Rfast [%] Max Total Error [%] Recommended Max Receiver Error [%] 8 96.00 103.90 +3.90/-4.00 ± 1.5 9 96.39 103.53 +3.53/-3.61 ± 1.5 10 96.70 103.23 +3.23/-3.30 ± 1.0 The recommendations for the maximum receiver baud rate error assume that the receiver and transmitter equally divide the maximum total error. 21.
Figure 21-9. Fractional baud rate example. BSEL=0 BSCALE=0 fBAUD=fPER/8 clkBAUD8 BSEL=3 BSCALE=-6 fBAUD=fPER/8.375 clkBAUD8 Extra clock cycle added BSEL=3 BSCALE=-4 fBAUD=fPER/9.5 clkBAUD8 Table 21-5. USART baud rate. Baud fOSC = 32.0000MHz CLK2X = 0 CLK2X = 1 rate (bps) BSEL BSCALE Error [%] BSEL BSCALE Error [%] 2400 12 6 0.2 12 7 0.2 4800 12 5 0.2 12 6 0.2 9600 12 4 0.2 12 5 0.2 34 2 0.8 34 3 0.8 138 0 -0.1 138 1 -0.1 12 3 0.2 12 4 0.2 34 1 -0.
Baud rate (bps) fOSC = 32.0000MHz CLK2X = 0 CLK2X = 1 BSEL BSCALE Error [%] BSEL BSCALE Error [%] 19 -4 -0.8 27 -3 -0.8 75 -6 -0.1 107 -5 -0.1 7 -4 0.6 15 -3 0.6 57 -7 0.1 121 -6 0.1 3 -5 -0.8 19 -4 -0.8 11 -7 -0.1 75 -6 -0.1 2.00M 0 0 0.0 1 0 0.0 2.304M – – – 3 -2 -0.8 47 -6 -0.1 2.5M – – – 19 -4 0.4 77 -7 -0.1 3.0M – – – 11 -5 -0.8 43 -7 -0.2 4.0M – – – 0 0 0.0 921.6k 1.382M 1.843M Max 2.0Mbps 4.0Mbps 21.
The USART transmitter in master SPI mode includes buffering, but the SPI module has no transmit buffer The USART receiver in master SPI mode includes an additional buffer level The USART in master SPI mode does not include the SPI write collision feature The USART in master SPI mode does not include the SPI double speed mode feature, but this can be achieved by configuring the baud rate generator accordingly Interrupt timing is not compatible Pin control differs due to the master-only
21.13 IRCOM Mode of Operation IRCOM mode can be enabled to use the IRCOM module with the USART. This enables IrDA 1.4 compliant modulation and demodulation for baud rates up to 115.2kbps. When IRCOM mode is enabled, double speed mode cannot be used for the USART. For devices with more than one USART, IRCOM mode can be enabled for only one USART at a time. For details, refer to “IRCOM - IR Communication Module” on page 285. 21.
21.15 Register Description 21.15.1 DATA – Data register Bit 7 6 5 4 3 2 1 0 RXB[[7:0] +0x00 TXB[[7:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART transmit data buffer register (TXB) and USART receive data buffer register (RXB) share the same I/O address and is referred to as USART data register (DATA). The TXB register is the destination for data written to the DATA register location.
Bit 4 – FERR: Frame Error The FERR flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. The bit is set if the received character had a frame error, i.e., the first stop bit was zero, and cleared when the stop bit of the received data is one. This bit is valid until the receive buffer (DATA) is read. FERR is not affected by setting the number of stop bits used, as it always uses only the first stop bit.
21.15.4 CTRLB – Control register B Bit 7 6 5 4 3 2 1 0 +0x04 – – – RXEN TXEN CLK2X MPCM TXB8 Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:5 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. Bit 4 – RXEN: Receiver Enable Setting this bit enables the USART receiver.
Table 21-7. CMODE bit settings. Notes: CMODE[1:0] Group Configuration Mode 00 ASYNCHRONOUS Asynchronous USART 01 SYNCHRONOUS Synchronous USART 10 IRCOM IRCOM(1) 11 MSPI Master SPI(2) 1. 2. See “IRCOM - IR Communication Module” on page 285 for full description on using IRCOM mode. See “USART in Master SPI Mode” on page 276 for full description of the master SPI operation. Bits 5:4 – PMODE[1:0]: Parity Mode These bits enable and set the type of parity generation according to Table 21-8.
Table 21-10. CHSIZE bit settings. CHSIZE[2:0] Group Configuration Character Size 000 5BIT 5-bit 001 6BIT 6-bit 010 7BIT 7-bit 011 8BIT 8-bit 100 Reserved 101 Reserved 110 Reserved 111 9BIT 9-bit Bit 2 – UDORD: Data Order This bit is only for master SPI mode, and this bit sets the frame format. When written to one, the lsb of the data word is transmitted first. When written to zero, the msb of the data word is transmitted first. The receiver and transmitter use the same setting.
21.16 Register Summary 21.16.1 Register Description - USART Address Name +0x00 +0x01 +0x02 +0x03 +0x04 +0x05 +0x06 +0x07 DATA STATUS Reserved CTRLA CTRLB CTRLC BAUDCTRL BAUDCTRL Bit 7 Bit 6 Bit 5 RXCIF TXCIF – – – – – – CMODE[1:0] Bit 4 DREIF FERR – – RXCINTLVL[1:0] – RXEN PMODE[1:0] Bit 3 Bit 2 Bit 1 DATA[7:0] BUFOVF PERR – – TXCINTLVL[1:0] TXEN CLK2X SBMODE BSEL[7:0] BSCALE[3:0] Bit 0 – RXB8 – – DREINTLVL[1:0] MPCM TXB8 CHSIZE[2:0] BSEL[11:8] Page 279 279 280 281 281 283 283 21.16.
22. IRCOM - IR Communication Module 22.1 Features Pulse modulation/demodulation for infrared communication IrDA compatible for baud rates up to 115.2kbps Selectable pulse modulation scheme 3/16 of the baud rate period Fixed pulse period, 8-bit programmable Pulse modulation disabled Built-in filtering Can be connected to and used by any USART 22.2 Overview XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates up to 115.2kbps.
For reception, a fixed programmable minimum high-level pulse width for the pulse to be decoded as a logical 0 is used. Shorter pulses will then be discarded, and the bit will be decoded to logical 1 as if no pulse was received. The module can only be used in combination with one USART at a time. Thus, IRCOM mode must not be set for more than one USART at a time. This must be ensured in the user software. 22.2.1 Event System Filtering The event system can be used as the receiver input.
22.3 Registers Description 22.3.1 TXPLCTRL – Transmitter Pulse Length Control Register Bit 7 6 5 +0x01 4 3 2 1 0 TXPLCTRL[7:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:0 – TXPLCTRL[7:0]: Transmitter Pulse Length Control This 8-bit value sets the pulse modulation scheme for the transmitter. Setting this register will have no effect if IRCOM mode is not selected by a USART.
Table 22-1. Event channel selection. 22.
23. AES and DES Crypto Engines 23.1 Features Data Encryption Standard (DES) CPU instruction Advanced Encryption Standard (AES) crypto module DES Instruction Encryption and decryption DES supported Encryption/decryption in 16 CPU clock cycles per 8-byte block AES crypto module Encryption and decryption Supports 128-bit keys Supports XOR data load mode to the state memory Encryption/decryption in 375 clock cycles per 16-byte block 23.
Figure 23-1. Register file usage during DES encryption/decryption. Register File data R0 data0 R1 data1 R2 data2 R3 data3 R4 data4 R5 data5 R6 data6 R7 data7 R8 key0 key R9 key1 R10 key2 R11 key3 R12 key4 R13 key5 R14 key6 R15 key7 R16 ... R31 Executing one DES instruction performs one round in the DES algorithm. Sixteen rounds must be executed in increasing order to form the correct DES ciphertext or plaintext.
23.4.1 Key and State Memory The AES key and state memory are both 16 x 8-bit memories that are accessible through the KEY and STATE registers, respectively. Each memory has two 4-bit address pointers used to address the memory for read and write, respectively. The initial value of the pointers is zero. After a read or write operation to the STATE or KEY register, the appropriate pointer is automatically incremented. Accessing (read or write) the control register (CTRL) will reset all pointers to zero.
In decryption mode, the key is the last subkey of the expanded key defined in the AES standard. In decryption mode, the key expansion procedure must be executed by software before operation with the AES crypto module so that the last subkey is ready to be loaded through the KEY register. Alternatively, this procedure can be run in hardware by using the AES crypto module to process a dummy data block in encryption mode using the same key.
23.5 Register Description – AES 23.5.1 CTRL – Control register Bit +0x00 7 6 5 4 3 2 1 0 START AUTO RESET DECRYPT – XOR – – Read/Write R/W R/W R/W R/W R R/W R R Initial Value 0 0 0 0 0 0 0 0 Bit 7 – START: Start/Run Setting this bit starts the encryption/decryption procedure, and this bit remains set while the encryption/decryption is ongoing. Writing this bit to zero will stop/abort any ongoing encryption/decryption process.
23.5.2 STATUS – AES Status register Bit 7 +0x01 6 5 4 3 2 1 0 ERROR – – – – – – SRIF Read/Write R/W R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 – ERROR: Error The ERROR flag indicates an illegal handling of the AES crypto module. The flag is set in the following cases: Setting START in the control register while the state memory and/or key memory are not fully loaded or read.
23.5.5 INTCTRL – Interrupt Control register Bit 7 6 5 4 3 2 1 0 +0x04 – – – – – – Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 INTLVL[1:0] Bit 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
23.6 Register summary – AES Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 bit 0 Page +0x00 CTRL START AUTO RESET DECRYPT – XOR – – 293 +0x01 STATUS ERROR – – – – – – SRIF 294 +0x02 STATE STATE[7:0] 294 +0x03 KEY KEY[7:0] 294 +0x04 INTCTRL – – – – – – +0x05 Reserved – – – – – – – – +0x06 Reserved – – – – – – – – +0x07 Reserved – – – – – – – – 23.7 INTLVL[1:0] 295 Interrupt vector summary Table 23-2.
24. CRC – Cyclic Redundancy Check Generator 24.
24.3 Operation The data source for the CRC module must be selected in software as either flash memory, the DMA channels, or the I/O interface. The CRC module then takes data input from the selected source and generates a checksum based on these data. The checksum is available in the CHECKSUM registers in the CRC module. When CRC-32 polynomial is used, the final checksum read is bit reversed and complemented (see Figure 24-1).
performed not only on communication data, but also on data in SRAM or I/O memory by passing these data through a DMA channel. If the latter is done, the destination register for the DMA data can be the data input (DATAIN) register in the CRC module. 24.6 CRC using the I/O Interface CRC can be performed on any data by loading them into the CRC module using the CPU and writing the data to the DATAIN register.
24.7 Register Description 24.7.1 CTRL – Control register Bit 7 +0x00 6 RESET[1:0] 5 4 CRC32 – 3 2 1 0 SOURCE[3:0] Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:6 – RESET[1:0]: Reset These bits are used to reset the CRC module, and they will always be read as zero. The CRC registers will be reset one peripheral clock cycle after the RESET[1] bit is set Table 24-1. CRC reset.
24.7.2 STATUS – Status register Bit 7 6 5 4 3 2 1 0 +0x02 – – – – – – ZERO BUSY Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. Bit 1 – ZERO: Checksum Zero This flag is set if the CHECKSUM is zero when the CRC generation is complete.
24.7.5 CHECKSUM1 – Checksum register 1 Bit 7 6 5 4 +0x05 3 2 1 0 CHECKSUM[15:8] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 4 3 2 1 0 Bit 7:0 – CHECKSUM[15:8]: Checksum byte 1 These bits hold byte 1 of the generated CRC. 24.7.
25. LCD – Liquid Crystal Display 25.
25.2.1 Definitions Several terms are used when describing LCD. The definitions in Table 25-1 are used throughout this document. Table 25-1. LCD definitions. LCD A passive display panel with terminals leading directly to a segment Segment (or pixel) A LCD panel active area within the display which can be turned “ON or “OFF”. This can be a single segment of a 7-segment character or a specific symbol (icon).
When a bit in the Display Memory is written to one, the corresponding segment will be energized (“ON”), and deenergized (“OFF”) when this bit is written to zero. To energize a segment, an absolute voltage above a certain threshold must be applied. This is done by setting the SEG pin to opposite phase when the corresponding COM pin is active. For a display with more than one common terminal, two (1/3 bias) additional voltage levels must be applied.
25.4 Mode of Operation 25.4.1 Static Duty and Static Bias If all segments on an LCD have one common electrode, then, each segment must have a unique segment terminal. This kind of display is driven with the waveform shown in Figure 25-3 on page 306. SEG0-COM0 is the voltage across a segment that is “ON”, and SEG1-COM0 is the voltage across a segment that is “OFF”. Figure 25-3. Driving an LCD With One Common Terminal 25.4.
Figure 25-5. Driving an LCD With Three Common Terminals 25.4.4 1/4 Duty and 1/3 Bias 1/3 bias is optimal for an LCD displays with four common terminals (1/4 duty). The waveform is shown in Figure 25-6 on page 307. SEG0-COM0 is the voltage across a segment that is ON” and SEG0-COM1 is the voltage across a segment that is “OFF”. Figure 25-6.
Figure 25-7. Low Power Waveform With Three Common Terminals 25.4.6 Operation in Sleep Modes The LCD will continue to operate in Idle mode, in Power-save mode and in Extended Standby mode (blinking included). 25.4.7 ASCII Character Mapping The LCD controller can automatically handle ASCII characters. Instead of setting and clearing segments of the digit, the user enters the ASCII code and the Digit Decoder updates itself the corresponding segment values in the Display Memory.
25.4.9 Display Blinking There are two ways to blink the display, controlled from software and controlled automatically by hardware. 25.4.9.1 Software Blinking Setting / clearing segment(s) in the Display Memory allows software blinking. To blink simultaneously all enabled segments, SEGON bit in CRTLA register can be used. The blink rate is software dependant. 25.4.9.2 Hardware Blinking Up to eight segments (pixels) can be configured to automatically blink.
Table 25-3. LCD power supply pins behavior. ENABLE(1) XBIAS(1) VLCD (pin) 0 x H.Z. BIAS2 H.Z. H.Z. 1 /3 VLCD 0 VLCD 1 Input for VLCD /3 VLCD (also in static mode) 1 1. CAPH / CAPL H.Z. 2 Notes: BIAS1 - Input for BIAS2 - H.Z. if static bias Pump voltage (also in static mode) - Input for BIAS1 - H.Z. if static bias H.Z. ENABLE and XBIAS bits of the CTRLA register. Figure 25-9.
25.4.12 Segment and Common Buses Swapping(1) Segment and/or common buses can be swapped (mirrored) to give more flexibility for LCD interconnects. The first segment (or common) terminal pin becomes the last one, and so on. It is very useful in Chip on Glass (CoG), Chip on Film (CoF) or Chip on Board (CoB) technologies. SEGSWP bit and COMSWP bit in the CRTLA register control the order of the respective terminal buses. Note: 1. Refer to specific device datasheet for availability of this feature. 25.4.
25.5 Register Description – LCD 25.5.1 CTRLA – Control register A Bit +0x00 7 6 5 4 3 2 1 0 ENABLE XBIAS DATLCK COMSWP SEGSWP CLRDT SEGON BLANK Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 – ENABLE: LCD Enable Writing this bit to one enables the LCD. By writing it to zero, the LCD is turned “OFF” immediately.
Table 25-5. Segment terminal bus reverse (examples) PMSK[5:0] Number of SEG SEGSWP = 0 SEGSWP = 1 000100 4 (SEG [39:4] unused), SEG[3:0] SEG[0:3], (SEG[4:39] unused) 001000 8 (SEG[39:8] unused), SEG[7:0] SEG[0:7], (SEG[8:39] unused) 010000 16 (SEG[39:16] unused), SEG[15:0] SEG[0:15], (SEG[16:39] unused) 101000 40 SEG[39:0] SEG[0:39] Note: 1. Refer to specific device datasheet for availability of this feature.
Bit 6:4 – CLKDIV[2:0]: LCD Clock Division The CLKDIV bit-field defines the division ratio in the clock divider. The various selections are shown in Table 25-7. This Clock Divider gives extra flexibility in frame rate setting. Frame rate equation: F clk LCD FrameRate = --------------------------------------------------------------- K N 1 + CLKDIV Where: N = prescaler divider (8 or 16). K = 8 for 1/4, 1/2 and static duty. K = 6 for 1/3 duty. Table 25-7. LCD clock divider (1/4 dyty).
Bits 1:0 – DUTY[1:0]: Duty Select(1) The DUTY bit-field defines the duty cycle. Common pins that are not used will be driven to ground. The different duty selections are shown in Table 25-9. Table 25-9. Duty cycle. Note: DUTY[1:0] Duty Bias COM pins Used 00 1/4 1/3 COM[0:3] 01 Static Static COM0 10 1/2 1/3 COM[0:1] 11 1/3 1/3 COM[0:2] 1. Refer to specific device datasheet for duty cycles availability (linked to the number of available common terminals). 25.5.
Bits 1:0 – FCINTLVL[1:0]: Interrupt Level This bit-field enables the LCD frame completed interrupt and selects the interrupt level as described in “Interrupts and Programmable Multilevel Interrupt Controller” on page 121. The enabled interrupt will be triggered when the FCIF flag in the INTFLAGS register is set. 25.5.
25.5.7 CTRLE – Control register E Bit 7 6 5 4 3 2 Read/Write R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 +0x06 1 0 R/W R/W R/W 0 0 0 BPS1[3:0] BPS0[3:0] Bits 7:4 – BPS1[3:0]: Blink Segment Selection 1 This bit-field defines the segment which is connected on SEG1 for blinking. Each bit of BPS1[3:0] corresponds to one of the common terminals. Bits 3:0 – BPS0[3:0]: Blink Segment Selection 0 This bit-field defines the segment which is connected on SEG0 for blinking.
Table 25-11. Type of digits. TDG[1:0] Note: 1. Digit Type 00 7-segment with 3 common terminals, COM[2:0] 01 7-segment with 4 common terminals, COM[3:0] 10 14-segment with 4 common terminals, COM[3:0] 11 16-segment with 3 common terminals, COM[2:0] Refer to specific device datasheet for “Type of Digit” availability. Bits 5:0 – STSEG[5:0]: Start Segment STSEG bit-field defines the first segment terminal used to write the decoded display.
The Table 25-12 on page 320, Table 25-13 on page 321 and Table 25-14 on page 322 show the DCODE[6:0] and display pattern. The table entry code, DCODE [6:0], is the 7-bit ASCII code of the digit.
Table 25-12. 7-segments Character Table.
Table 25-13. 14-segments Character Table.
Table 25-14. 16-segments Character Table.
25.5.11 DATA – LCD Data Memory Mapping The Display Memory provides access to control the “ON/OFF” state for segments.
25.6 Register Summary – LCD Address Name Bit 7 Bit 6 Bit 5 Bit 4 +0x24 to +0x23 +0x22 +0x21 +0x20 +0x1F +0x1E +0x1D +0x1C +0x1B +0x1A +0x19 +0x18 +0x17 +0x16 +0x15 +0x14 +0x13 +0x12 +0x11 +0x10 +0x0A to +0x09 +0x08 +0x07 +0x06 +0x05 +0x04 +0x03 +0x02 +0x01 +0x00 Reserved DATA19 DATA18 DATA17 DATA16 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Reserved CTRLH CTRLG CTRLF CTRLE CTRLD INTFLAGS INTCTRL CTRLC CTRLB CTRLA – – – – 25.
26. ADC – Analog-to-Digital Converter 26.1 Features 12-bit resolution Up to 300 thousand samples per second Down to 2.3μs conversion time with 8-bit resolution Down to 3.
Figure 26-1. ADC overview. VIN S&H ADC Σ VOUT 2x DAC 2 bits ADC0 • • • ADC15 VINP Stage 1 2 Internal signals < > Stage 2 2 Threshold (Int Req) CH0 Result clkADC Digital Correction Logic ADC0 • • • ADC7 VINN Internal 1.00V Internal VCC/1.6V Internal VCC/2 AREFA AREFB CH0.CTRL CH0.MUXCTRL 26.
Figure 26-2. Differential measurement without gain. ADC0 • • • ADC15 + ADC0 • • • ADC3 GND INTGND - 26.3.2 Differential Input with Gain When differential input with gain is enabled, all input pins can be selected as positive input, and input pins 4 to 7 can be selected as negative input. When gain is enabled, the differential input is first sampled and amplified by the gain stage before the result is converted. The ADC must be in signed mode when differential input with gain is used.
Figure 26-4. Single-ended measurement in signed mode. ADC0 • •• + ADC ADC15 - In unsigned mode, the negative input is connected to half of the voltage reference (VREF) voltage minus a fixed offset. The nominal value for the offset is: V = VREF 0.05 Since the ADC is differential, the input range is VREF to zero for the positive single-ended input.
Figure 26-6. Internal measurements in single-ended signed mode. TEMP REF + BANDGAP REF ADC VCC SCALED - To measure the internal signals in unsigned mode, the negative input is connected to a fixed value given by the formula below, which is half of the voltage reference (VREF) minus a fixed offset, as it is for single-ended unsigned input. Refer to Figure 26-11 on page 331 for details. VINN = VREF/2 - V Figure 26-7. Internal measurements in unsigned mode.
26.6 Conversion Result The result of the analog-to-digital conversion is written to the channel result register. The ADC is either in signed or unsigned mode. This setting is global for the ADC and for the ADC channel. In signed mode, negative and positive results are generated. Signed mode must be used when the ADC channel is set up for differential measurements. In unsigned mode, only single-ended or internal signals can be measured.
Figure 26-10.Signed single-ended and internal input, input range, and result representation. VREF VINP VINN = GND 0V -VREF Dec 2047 2046 2045 ... 3 2 1 0 -1 -2 ... -2045 -2046 -2047 -2048 Hex 7FF 7FE 7FD ... 3 2 1 0 FFF FFE ... 803 802 801 800 Binary 0111 1111 1111 0111 1111 1110 0111 1111 1101 ... 0000 0000 0011 0000 0000 0010 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 ...
Figure 26-12.ADC prescaler. CLK/512 CLK/256 CLK/128 CLK/64 CLK/32 CLK/16 CLK/8 9-bit ADC Prescaler CLK/4 ClkPER PRESCALER[2:0] ClkADC The propagation delay of an ADC measurement is given by: RESOLUTION + 1 1 + ------------------------------------------------- + GAIN 2 Propagation Delay = -------------------------------------------------------------------------------f ADC RESOLUTION is the resolution, 8 or 12 bits.
Figure 26-14.ADC timing for one single conversion with increased sampling time (SAMPVAL = 6). 1 2 3 4 5 6 7 8 10 9 clkADC START ADC SAMPLE IF CONVERTING BIT msb 9 10 8 7 6 5 3 4 2 1 lsb 26.9.2 Single Conversion with Gain Figure 26-15 on page 333 to Figure 26-17 on page 334 show the ADC timing for one single conversion with various gain settings. As seen in the “Overview” on page 325, the gain stage is built into the ADC.
Figure 26-17.ADC timing for one single conversion with 64x gain. 1 2 3 4 5 6 7 8 9 10 clkADC START ADC SAMPLE AMPLIFY IF CONVERTING BIT msb 10 9 8 7 6 5 4 3 2 1 lsb 26.10 ADC Input Model The voltage input must charge the sample and hold (S/H) capacitor in the ADC in order to achieve maximum accuracy. Seen externally, the ADC input consists of an input resistance (Rin = Rchannel + Rswitch) and the S/H capacitor (Csample).
26.11 DMA Transfer The DMA controller can be used to transfer ADC conversion results to memory or other peripherals. A new conversion result can trigger a DMA transaction. Refer to “DMAC - Direct Memory Access Controller” on page 49 for more details on DMA transfers. 26.12 Interrupts and Events The ADC can generate interrupt requests and events. The ADC channel has individual interrupt settings and interrupt vectors.
26.15 Register Description – ADC 26.15.1 CTRLA – Control register A Bit 7 6 5 4 3 2 1 0 +0x00 – – – – – CH0START FLUSH ENABLE Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. Bit 2 – CH0START: Channel Start Single Conversion Setting this bit will start an ADC conversion.
Bit 4 – CONVMODE: Conversion Mode This bit controls whether the ADC will work in signed or unsigned mode. By default, this bit is cleared and the ADC is configured for unsigned mode. When this bit is set, the ADC is configured for signed mode. Bit 3 – FREERUN: Free Running Mode This bit controls the free running mode for the ADC. Once a conversion is finished, the next input will be sampled and converted.
Bit 3:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. Bit 1 – BANDGAP: Bandgap Enable Setting this bit enables the bandgap for ADC measurement. Note that if any other functions are already using the bandgap, this bit does not need to be set when the internal 1.00V reference is used for another ADC or if the brownout detector is enabled.
EVACT[2:0] Group Configuration 101 – 110 SYNCSWEEP 111 – Event Input Operation Mode Reserved The ADC is flushed and restarted for accurate timing Reserved 26.15.5 PRESCALER – Clock Prescaler register Bit 7 6 5 4 3 +0x04 – – – – – Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 2 1 0 PRESCALER[2:0] Bit 7:3 – Reserved These bits are unused and reserved for future use.
26.15.7 TEMP – Temporary register Bit 7 6 5 4 +0x07 3 2 1 0 TEMP[7:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:0 – TEMP[7:0]: Temporary bits This register is used when reading 16-bit registers in the ADC controller. The high byte of the 16-bit register is stored here when the low byte is read by the CPU. This register can also be read and written from the user software.
26.15.11CH0RESH – Channel 0 Result register High The CH0RESL and CH0RESH register pair represents the 16-bit value, CH0RES. For details on reading 16-bit registers, refer to “Accessing 16-bit Registers” on page 11. Bit 7 6 5 4 12-bit, right – – – – 8-bit – – – – – – – – Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 12-bit, left 3 2 1 0 CHRES[11:4] CHRES[11:8] 26.15.11.
26.15.13 CMPH – Compare register High The CMPH and CMPL register pair represents the 16-bit value, CMP. For details on reading and writing 16-bit registers, refer to “Accessing 16-bit Registers” on page 11. Bit 7 6 5 4 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 +0x19 CMP[15:0] Bit 7:0 – CMP[15:0]: Compare Value High byte These are the eight msbs of the 16-bit ADC compare value.
Table 26-7. ADC gain factor GAIN[2:0] Group Configuration Gain Factor 000 1X 1x 001 2X 2x 010 4X 4x 011 8X 8x 100 16X 16x 101 32X 32x 110 64X 64x 111 DIV2 ½x Bit 1:0 – INPUTMODE[1:0]: Channel Input Mode These bits define the channel mode. Table 26-8. Channel input modes, CONVMODE=0 (unsigned mode).
Bit 6:3 – MUXPOS[3:0]: MUX Selection on Positive ADC Input These bits define the MUX selection for the positive ADC input. Table 26-10 and Table 26-11 show the possible input selection for the different input modes. Table 26-10. ADC MUXPOS configuration when INPUTMODE[1:0] = 00 (internal) is used. MUXPOS[3:0] Group Configuration Description 0000 TEMP Temperature reference 0001 BANDGAP Bandgap voltage 0010 SCALEDVCC 1/10 scaled VCC 0011 – Reserved 0100-1111 – Reserved Table 26-11.
MUXPOS[3:0] Group Configuration Description 0011 PIN3 ADC3 pin 0100 PIN4 ADC4 pin 0101 PIN5 ADC5 pin 0110 PIN6 ADC6 pin 0111 PIN7 ADC7 pin 1XXX – Reserved Depending on the device pin count and feature configuration, the actual number of analog input pins may be less than 16. Refer to the device datasheet and pin-out description for details.
26.16.3 INTCTRL – Interrupt Control registers Bit 7 6 5 4 3 +0x02 – – – – INTMODE[1:0} Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 2 1 0 INTLVL[1:0] Bits 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. Bit 3:2 – INTMODE: Interrupt Mode These bits select the interrupt mode for the channel according to Table 26-5. Table 26-15.
26.16.5 RESH – Result register High For all result registers and with any ADC result resolution, a signed number is represented in 2’s complement form, and the msb represents the sign bit. The RESL and RESH register pair represents the 16-bit value, ADCRESULT. Reading and writing 16-bit values require special attention. Refer to “Accessing 16-bit Registers” on page 11 for details.
26.16.7 SCAN – Input Channel Scan register Scan is enabled when COUNT is set differently than 0. Bit 7 6 5 4 3 2 Read/Write R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 +0x06 1 0 R/W R/W R/W 0 0 0 OFFSET[3:0] COUNT[3:0] Bit 7:4 – OFFSET[3:0]: Positive MUX Setting Offset The channel scan is enabled when COUNT != 0 and this register contains the offset for the next input source to be converted on ADC channel. The actual MUX setting for positive input equals MUXPOS + OFFSET.
26.17 Register Summary – ADC This is the register summary when the ADC is configured to give standard 12-bit results. The register summaries for 8-bit and 12bit left adjusted will be similar, but with some changes in the result registers, CH0RESH and CH0RESL.
27. AC – Analog Comparator 27.
Figure 27-1. Analog comparator overview. Pin Input + AC0OUT AC0 Pin Input Hysteresis Enable Voltage Scaler ACnCTRL ACnMUXCTRL Bandgap Interrupt Mode Interrupt Sensititivity Control & Window Function WINCTRL Enable Interrupts Events Hysteresis + Pin Input AC1OUT AC1 Pin Input 27.3 Input Sources Each analog comparator has one positive and one negative input. Each input may be chosen from a selection of analog input pins and internal inputs such as a VCC voltage scaler.
27.6 Window Mode Two analog comparators on the same port can be configured to work together in window mode. In this mode, a voltage range is defined, and the analog comparators give information about whether an input signal is within this range or not. Figure 27-2. The Analog comparators in window mode. + AC0 Upper limit of window Interrupt sensitivity control Input signal Interrupts Events + AC1 Lower limit of window 27.
27.8 Register Description 27.8.1 ACnCTRL – Analog Comparator n Control register Bit 7 +0x00 / +0x01 6 5 INTMODE[1:0] 4 INTLVL[1:0] 3 2 – HYSMODE[2:0] 1 0 ENABLE Read/Write R/W R/W R/W R/W R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:6 – INTMODE[1:0]: Interrupt Modes These bits configure the interrupt mode for analog comparator n according to Table 27-1. Table 27-1. Interrupt settings.
27.8.2 ACnMUXCTRL – Analog Comparator n Mux Control register Bit 7 6 +0x02 / +0x03 – – Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 5 4 3 2 MUXPOS[2:0] 1 0 MUXNEG[2:0] Bit 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
27.8.3 CTRLA – Control register A Bit 7 6 5 4 3 2 1 0 +0x04 – – – – – – AC1OUT AC0OUT Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. Bit 1 – AC1OUT: Analog Comparator 1 Output Setting this bit makes the output of AC1 available on pin 6 of the port.
Table 27-5. Window mode interrupt settings.
This flag is automatically cleared when the analog comparator 1 interrupt vector is executed. The flag can also be cleared by writing a one to its bit location. Bit 0 – AC0IF: Analog Comparator 0 Interrupt Flag This is the interrupt flag for AC0. AC0IF is set according to the INTMODE setting in the corresponding “ACnCTRL – Analog Comparator n Control register” on page 353. This flag is automatically cleared when the analog comparator 0 interrupt vector is executed.
27.
28. IEEE 1149.1 JTAG Boundary Scan Interface 28.1 Features • • • • • • 28.2 JTAG (IEEE Std. 1149.
Figure 28-1. TAP controller state diagram. The TAP controller is a 16-state, finite state machine that controls the operation of the boundary scan circuitry. The state transitions shown in Figure 28-1 depend on the signal present on TMS (shown adjacent to each state transition) at the time of the rising edge on TCK. The initial state after a power-on reset is the test logic reset state.
As shown in the state diagram, the run test/idle state need not be entered between selecting JTAG instructions and using data registers. Note: Independently of the initial state of the TAP controller, the test logic reset state can always be entered by holding TMS high for five TCK clock periods. 28.4 JTAG Instructions The instruction register is four bits wide. Listed below are the JTAG instructions for boundary scan operation and the PDICOM instruction used for accessing the PDI in JTAG mode.
The active states are: Capture DR: Loads a zero into the bypass register Shift DR: The bypass register cell between TDI and TDO is shifted 28.4.5 CLAMP; 0x4 CLAMP is an optional instruction that allows the state of the input/output pins to be determined from the preloaded output latches. The instruction allows static pin values to be applied via the boundary scan registers while bypassing these registers in the scan path, efficiently shortening the total length of the serial test path.
Figure 28-2. Boundary scan cell for bi-directional port pin. Mode Output Control (DIR) Shift DR To next cell 0 1 0 D Q D Q 1 Output Data (IN) Pn 0 En 1 0 D Q D Q 1 Input Data (IN) From last cell Clock DR Update DR 28.5.2 Scanning the PDI Pins Two observe-only cells are inserted to make the combined RESET and PDI_CLK pin and the PDI_DATA pin observable. Even though the PDI_DATA pin is bidirectional, it is only made observable in order to avoid any extra logic on the PDI_DATA output path.
Bypass register (Ref: register A in Figure 28-4 on page 364). Device identification register (Ref: register C in Figure 28-4 on page 364). Boundary scan chain (Ref: register D in Figure 28-4 on page 364). PDICOM data register (Ref: register B in Figure 28-4 on page 364) Figure 28-4. JTAG data register overview. PDI to all TCK registers JTAG TCK D TAP CTRL JTAG Boundary-scan chain D D TDO I/O PORTS D TMS Internal registers A D D B B C C B C TDI C D D D D D 28.6.
28.6.4 PDICOM Data Register The PDICOM data register is a 9-bit wide register used for serial-to-parallel and parallel-to-serial conversions of data between the JTAG TAP and the PDI. For details, refer to “Program and Debug Interface” on page 408.
29. Program and Debug Interface 29.
Figure 29-1. The PDI and PDI physical layers and closely related modules (grey). PDIBUS Program and Debug Interface (PDI) Internal Interfaces OCD PDI_CLK PDI_DATA PDI Physical (physical layer) PDI Controller NVM Memories NVM Controller 29.3 PDI Physical The PDI physical layer handles the low-level serial communication. It uses a bidirectional, half-duplex, synchronous serial receiver and transmitter (just as a USART in USRT mode).
Figure 29-3. PDI physical layer enable sequence. Disable RESET function on Reset (PDI_CLK) pin Activate PDI PDI_DATA PDI_CLK The Reset pin is sampled when the PDI interface is enabled. The reset register is then set according to the state of the Reset pin, preventing the device from running code after the reset functionality of this pin is disabled. 29.3.2 Disabling If the clock frequency on PDI_CLK is lower than approximately 10kHz, this is regarded as inactivity on the clock line.
29.3.4 Serial Transmission and Reception The PDI physical layer is either in transmit (TX) or receive (RX) mode. By default, it is in RX mode, waiting for a start bit. The programmer and the PDI operate synchronously on the PDI_CLK provided by the programmer. The dependency between the clock edges and data sampling or data change is fixed.
The external programmer will loose control of the PDI_DATA line at the point where the PDI changes from RX to TX mode. The guard time relaxes this critical phase of the communication. When the programmer changes from RX mode to TX mode, a single IDLE bit, at minimum, should be inserted before the start bit is transmitted. 29.3.
29.4 PDI Controller The PDI controller performs data transmission/reception on a byte level, command decoding, high-level direction control, control and status register access, exception handling, and clock switching (PDI_CLK or TCK). The interaction between an external programmer and the PDI controller is based on a scheme where the programmer transmits various types of requests to the PDI controller, which in turn responds according to the specific request.
29.4.5.1 LDS - Load Data from PDIBUS Data Space using Direct Addressing The LDS instruction is used to load data from the PDIBUS data space for read out. The LDS instruction is based on direct addressing, which means that the address must be given as an argument to the instruction. Even though the protocol is based on byte-wise communication, the LDS instruction supports multiple-byte addresses and data access.
The REPEAT instruction cannot be repeated. The KEY instruction cannot be repeated, and will override the current value of the repeat counter register. 29.4.6 Instruction Set Summary The PDI instruction set summary is shown in Figure 29-10 on page 373. Figure 29-10.PDI instruction set summary.
29.5.2 Pointer Register The pointer register is used to store an address value that specifies locations within the PDIBUS address space. During direct data access, the pointer register is updated by the specified number of address bytes given as operand bytes to an instruction. During indirect data access, addressing is based on an address already stored in the pointer register prior to the access itself. Indirect data access can be optionally combined with pointer register post-increment.
29.6 Register Description – PDI Control and Status Registers The PDI control and status registers are accessible in the PDI control and status register space (CSRS) using the LDCS and STCS instructions. The CSRS contains registers directly involved in configuration and status monitoring of the PDI itself. 29.6.
Table 29-1. Guard time settings. 29.
30. Memory Programming 30.
programming. For more details, refer to “Register Description” on page 395. 30.4 NVM Commands The NVM controller has a set of commands used to perform tasks on the NVM. This is done by writing the selected command to the NVM command register. In addition, data and addresses must be read/written from/to the NVM data and address registers for memory read/write operations.
30.6 Flash and EEPROM Page Buffers The flash memory is updated page by page. The EEPROM can be updated on a byte-by-byte and page-by-page basis. flash and EEPROM page programming is done by first filling the associated page buffer, and then writing the entire page buffer to a selected page in flash or EEPROM. The size of the page and page buffers depends on the flash and EEPROM size in each device, and details are described in the device datasheet. 30.6.
Alternative 1: Fill the flash page buffer Perform a flash page erase Perform a flash page write Alternative 2: Fill the flash page buffer Perform an atomic page erase and write Alternative 3, fill the buffer after a page erase: Perform a flash page erase Fill the flash page buffer Perform a flash page write The NVM command set supports both atomic erase and write operations, and split page erase and page write commands.
Depending on the programming operation, if any of these VCC voltage levels are reached, the programming sequence will be aborted immediately. If this happens, the NVM programming should be restarted when the power is sufficient again, in case the write sequence failed or only partly succeeded. 30.10 CRC Functionality It is possible to run an automatic cyclic redundancy check (CRC) on the flash program memory.
For flash read operations (ELPM and LPM), one byte is read at a time. For this, the least-significant bit (bit 0) in the Zpointer is used to select the low byte or high byte in the word address. If this bit is 0, the low byte is read, and if this bit is 1 the high byte is read. The size of FWORD and FPAGE will depend on the page and flash size in the device. Refer to each device’s datasheet for details.
Table 30-2. Flash self-programming commands.
30.11.2.2 Erase Flash Page Buffer The erase flash page buffer command is used to erase the flash page buffer. 1. Load the NVM CMD with the erase flash page buffer command. 2. Set the command execute bit (NVMEX) in the NVM control register A (NVM CTRLA). This requires the timed CCP sequence during self-programming. The NVM busy (BUSY) flag in the NVM status register (NVM STATUS) will be set until the page buffer is erased. 30.11.2.
3. Execute the SPM instruction. This requires the timed CCP sequence during self-programming. The BUSY flag in the STATUS register will be set until the operation is finished. The CPU will be halted during the complete execution of the command. 30.11.2.8 Erase Application Section / Boot Loader Section Page The erase application section page erase and erase boot loader section page commands are used to erase one page in the application section or boot loader section. 1.
30.11.2.12 Erase User Signature Row The erase user signature row command is used to erase the user signature row. 1. Load the NVM CMD register with the erase user signature row command. 2. Execute the SPM instruction. This requires the timed CCP sequence during self-programming. The BUSY flag in the NVM STATUS register will be set, and the CPU will be halted until the erase operation is finished. The user signature row is NRWW. 30.11.2.
30.11.3.1 Write Lock Bits The write lock bits command is used to program the boot lock bits to a more secure settings from software. 1. Load the NVM DATA0 register with the new lock bit value. 2. Load the NVM CMD register with the write lock bit command. 3. Set the CMDEX bit in the NVM CTRLA register. This requires the timed CCP sequence during self-programming. The BUSY flag in the NVM STATUS register will be set until the command is finished.
Figure 30-2. I/O mapped EEPROM addressing. PAGEMSB BIT BYTEMSB PAGE ADDRESS WITHIN THE EEPROM E2PAGE 0 E2BYTE E2PAGE NVM ADDR BYTE ADDRESS WITHIN A PAGE EEPROM MEMORY 00 E2BYTE PAGE 00 DATA BYTE PAGE 01 01 02 02 E2PAGEEND E2END When EEPROM memory mapping is enabled, loading a data byte into the EEPROM page buffer can be performed through direct or indirect store instructions.
CMD[6:0] CPU Halted Change Protected NVM Busy Address Pointer Data Register Group Configuration Description Trigger 0x32 ERASE_EEPROM_PAGE Erase EEPROM page CMDEX N Y Y ADDR - 0x34 WRITE_EEPROM_PAGE Write EEPROM page CMDEX N Y Y ADDR - 0x35 ERASE_WRITE_EEPROM_PAGE Erase and write EEPROM page CMDEX N Y Y ADDR - 0x30 ERASE_EEPROM Erase EEPROM CMDEX N Y Y - - 0x06 READ_EEPROM Read EEPROM CMDEX N Y N ADDR EEPROM DATA0 30.11.5.
30.11.5.6 Erase EEPROM The erase EEPROM command is used to erase all locations in all EEPROM pages that are loaded and tagged in the EEPROM page buffer. 1. Set up the NVM CMD register to the erase EPPROM command. 2. Set the CMDEX bit in the NVM CTRLA register. This requires the timed CCP sequence during self-programming. The BUSY flag in the NVM STATUS register will be set until the operation is finished. 30.11.5.7 Read EEPROM The read EEPROM command is used to read one byte from the EEPROM. 1.
Figure 30-3. Memory map for PDI accessing the data and program memories. TOP=0x1FFFFFF FLASH_BASE EPPROM_BASE FUSE_BASE DATAMEM_BASE = 0x0800000 = 0x08C0000 = 0x08F0020 = 0x1000000 APP_BASE = FLASH_BASE BOOT_BASE = FLASH_BASE + SIZE_APPL PROD_SIGNATURE_BASE = 0x008E0200 USER_SIGNATURE_BASE = 0x008E0400 DATAMEM (mapped IO/SRAM) 16 MB 0x1000000 0x08F0020 0x08E0200 0x08C1000 0x08C0000 FUSES SIGNATURE ROW EEPROM BOOT SECTION APPLICATION SECTION 0x0800000 16 MB 0x0000000 1 BYTE 30.12.
writing data or program memory addresses from the PDI refer to the memory map shown in Figure 30-3 on page 391. The PDI uses byte addressing, and hence all memory addresses must be byte addresses. When filling the flash or EEPROM page buffers, only the least-significant bits of the address are used to determine locations within the page buffer. Still, the complete memory mapped address for the flash or EEPROM page is required to ensure correct address mapping.
Change Protected CMD[6:0] Commands / Operation Trigger 0x39 Boot loader section CRC NVMAA Y Y (2) Production Signature (Calibration) NVM Busy and User Signature Sections 0x01 Read user signature row PDI read N N 0x18 Erase user signature row PDI write N Y 0x1A Write user signature row PDI write N Y 0x02 Read calibration row PDI read N N Fuses and Lock Bits 0x07 Read fuse PDI read N N 0x4C Write fuse PDI write N Y 0x08 Write lock bits CMDEX Y Y EEPROM Page Buff
30.12.3.3 Erase Page Buffer The erase flash page buffer and erase EEPROM page buffer commands are used to erase the flash and EEPROM page buffers. 1. Load the NVM CMD register with the erase flash/EEPROM page buffer command. 2. Set the CMDEX bit in the NVM CTRLA register. The BUSY flag in the NVM STATUS register will be set until the operation is completed. 30.12.3.
30.12.3.9 Application / Boot Section CRC The application section CRC and boot loader section CRC commands can be used to verify the content of the selected section after programming. 1. Load the NVM CMD register with application/ boot loader section CRC command. 2. Set the CMDEX bit in the NVM CTRLA register. This requires the timed CCP sequence during self-programming. The BUSY flag in the NVM STATUS register will be set until the operation is finished.
31. Peripheral Module Address Map The address maps show the base address for each peripheral and module in XMEGA. All peripherals and modules are not present in all XMEGA devices, refer to device data sheet for the peripherals module address map for a specific device.
32.
Mnemonics Operands Description Operation Flags #Clocks ICALL Indirect Call to (Z) PC(15:0) PC(21:16) Z, 0 None 2 / 3(1) EICALL Extended Indirect Call to (Z) PC(15:0) PC(21:16) Z, EIND None 3(1) call Subroutine PC k None 3 / 4(1) RET Subroutine Return PC STACK None 4 / 5(1) RETI Interrupt Return PC STACK I 4 / 5(1) if (Rd = Rr) PC PC + 2 or 3 None 1/2/3 CALL k CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry
Mnemonics Operands Description Flags #Clocks LDS Rd, k Load Direct from data space Rd (k) None 2(1)(2) LD Rd, X Load Indirect Rd (X) None 1(1)(2) LD Rd, X+ Load Indirect and Post-Increment Rd X (X) X+1 None 1(1)(2) LD Rd, -X Load Indirect and Pre-Decrement X X - 1, Rd (X) X-1 (X) None 2(1)(2) LD Rd, Y Load Indirect Rd (Y) (Y) None 1(1)(2) LD Rd, Y+ Load Indirect and Post-Increment Rd Y (Y) Y+1 None 1(1)(2) LD Rd, -Y Load Indirect
Mnemonics Operands Description IN Rd, A In From I/O Location OUT A, Rr Out To I/O Location PUSH Rr Push Register on Stack POP Rd XCH Operation Flags #Clocks Rd I/O(A) None 1 I/O(A) Rr None 1 STACK Rr None 1(1) Pop Register from Stack Rd STACK None 2(1) Z, Rd Exchange RAM location Temp Rd (Z) Rd, (Z), Temp None 2 LAS Z, Rd Load and Set RAM location Temp Rd (Z) Rd, (Z), Temp v (Z) None 2 LAC Z, Rd Load and Clear RAM location Temp Rd
Mnemonics Operands Description Operation Flags #Clocks SEV Set Two’s Complement Overflow V 1 V 1 CLV Clear Two’s Complement Overflow V 0 V 1 SET Set T in SREG T 1 T 1 CLT Clear T in SREG T 0 T 1 SEH Set Half Carry Flag in SREG H 1 H 1 CLH Clear Half Carry Flag in SREG H 0 H 1 None 1 None 1 MCU control instructions BREAK Break NOP No Operation SLEEP Sleep (see specific descr. for Sleep) None 1 WDR Watchdog Reset (see specific descr.
33. Datasheet Revision History Please note that the referring page numbers in this section are referring to this document. The referring revision in this section are referring to the document revision. 33.1 8291B – 01/2013 1. Added XMEGA B feature overview inTable 2-1 on page 5. 2. References to Calibration Row updated to Production Signature Row for consistency. 3. Added reference to “NVM Flash Commands” on page 382 in “Production Signature Row” on page 22. 4.
33.2 26. Updated “Synchronous Sampling” on page 335. 27 Updated description of “Bit 3:0 – COUNT[3:0]: Number of Input Channels Included in Scan” in “SCAN – Input Channel Scan register” on page 348 28. Updated Analog Comparator overview block diagram in Figure 27-1 on page 351. 8291A – 07/2011 1.
Table of Contents 1. About the Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1 1.2 1.3 Reading the Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Recommended Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Overview . . . . . . . . . . . . . . . .
5. DMAC - Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . 49 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DMA Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4 8.5 8.6 8.7 8.8 8.9 Power Reduction Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Minimizing Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Register Description – Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Register Description – Power Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Register Summary - Sleep . . . . . . . . . . . . . . . . . . . . . . . . . .
12.16 Register Summary – Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 12.17 Register Summary – Virtual Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 12.18 Interrupt Vector Summary – Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 13. TC0/1 – 16-bit Timer/Counter Type 0 and 1 . . . . . . . . . . . . . . . . . 151 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 13.10 13.11 13.12 13.13 13.14 Features . . . . . . . . . . .
17.2 17.3 17.4 17.5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Vector Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 203 208 208 18. USB – Universal Serial Bus Interface . . .
21. USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 21.1 21.2 21.3 21.4 21.5 21.6 21.7 21.8 21.9 21.10 21.11 21.12 21.13 21.14 21.15 21.16 21.17 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26. ADC – Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . 325 26.1 26.2 26.3 26.4 26.5 26.6 26.7 26.8 26.9 26.10 26.11 26.12 26.13 26.14 26.15 26.16 26.17 26.18 26.19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30.2 30.3 30.4 30.5 30.6 30.7 30.8 30.9 30.10 30.11 30.12 30.13 30.14 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NVM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NVM Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NVM Controller Busy Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XMEGA B [DATASHEET] 8291B–AVR–01/2013 412
XMEGA B [DATASHEET] 8291B–AVR–01/2013 413
XMEGA B [DATASHEET] 8291B–AVR–01/2013 414
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